Commit af3847a7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2022-05-05' of... 

Merge tag 'drm-intel-gt-next-2022-05-05' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

UAPI Changes:

- Add kerneldoc for engine class enum (Matt Roper)
- Add compute engine ABI (Matt Roper)

Driver Changes:

- Define GuC firmware version for DG2 (John Harrison)
- Clear SET_PREDICATE_RESULT prior to executing the ring (Chris Wilson)
- Fix race in __i915_vma_remove_closed (Karol Herbst)

- Add register for compute engine's MMIO-based TLB invalidation (Matt Roper)
- Xe_HP SDV and DG2 have up to 4 CCS engines (Daniele Ceraolo Spurio)
- Add initial Ponte Vecchio definitions (Stuart Summers)
- Document the eviction of the Flat-CCS objects (Ramalingam C)

- Use existing uncore helper to read gpm_timestamp (Umesh Nerlige Ramappa)
- Fix issue with LRI relative addressing (Akeem G Abodunrin)
- Skip poisoning SET_PREDICATE_RESULT on dg2 (Chris Wilson)
- Optimize the ccs_sz calculation per chunk (Ramalingam C)
- Remove superfluous string helper include (Jani Nikula)
- Fix assert in i915_ggtt_pin (Tvrtko Ursulin)
- Use IOMEM_ERR_PTR() directly (Kefeng Wang)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YnNxCm1pyflu3taj@tursulin-mobl2
parents 97ab5308 1df1c79c

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+54 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


#include "gen8_engine_cs.h"

#include "i915_drv.h"

#include "intel_engine_regs.h"

#include "intel_gpu_commands.h"

#include "intel_lrc.h"

#include "intel_ring.h"
@@ -385,6 +386,59 @@ int gen8_emit_init_breadcrumb(struct i915_request *rq) 
	return 0;

}



static int __gen125_emit_bb_start(struct i915_request *rq,

				  u64 offset, u32 len,

				  const unsigned int flags,

				  u32 arb)

{

	struct intel_context *ce = rq->context;

	u32 wa_offset = lrc_indirect_bb(ce);

	u32 *cs;



	cs = intel_ring_begin(rq, 12);

	if (IS_ERR(cs))

		return PTR_ERR(cs);



	*cs++ = MI_ARB_ON_OFF | arb;



	*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |

		MI_SRM_LRM_GLOBAL_GTT |

		MI_LRI_LRM_CS_MMIO;

	*cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0));

	*cs++ = wa_offset + DG2_PREDICATE_RESULT_WA;

	*cs++ = 0;



	*cs++ = MI_BATCH_BUFFER_START_GEN8 |

		(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));

	*cs++ = lower_32_bits(offset);

	*cs++ = upper_32_bits(offset);



	/* Fixup stray MI_SET_PREDICATE as it prevents us executing the ring */

	*cs++ = MI_BATCH_BUFFER_START_GEN8;

	*cs++ = wa_offset + DG2_PREDICATE_RESULT_BB;

	*cs++ = 0;



	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;



	intel_ring_advance(rq, cs);



	return 0;

}



int gen125_emit_bb_start_noarb(struct i915_request *rq,

			       u64 offset, u32 len,

			       const unsigned int flags)

{

	return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);

}



int gen125_emit_bb_start(struct i915_request *rq,

			 u64 offset, u32 len,

			 const unsigned int flags)

{

	return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);

}



int gen8_emit_bb_start_noarb(struct i915_request *rq,

			     u64 offset, u32 len,

			     const unsigned int flags)

drivers/gpu/drm/i915/gt/gen8_engine_cs.h

+7 −0
Original line number Diff line number Diff line
@@ -31,6 +31,13 @@ int gen8_emit_bb_start(struct i915_request *rq, 
		       u64 offset, u32 len,

		       const unsigned int flags);



int gen125_emit_bb_start_noarb(struct i915_request *rq,

			       u64 offset, u32 len,

			       const unsigned int flags);

int gen125_emit_bb_start(struct i915_request *rq,

			 u64 offset, u32 len,

			 const unsigned int flags);



u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

drivers/gpu/drm/i915/gt/intel_engine_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -148,6 +148,7 @@ 
		(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \

		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))



#define RING_PREDICATE_RESULT(base)		_MMIO((base) + 0x3b8) /* gen12+ */

#define MI_PREDICATE_RESULT_2(base)		_MMIO((base) + 0x3bc)

#define   LOWER_SLICE_ENABLED			(1 << 0)

#define   LOWER_SLICE_DISABLED			(0 << 0)
@@ -193,6 +194,7 @@ 
#define RING_TIMESTAMP_UDW(base)		_MMIO((base) + 0x358 + 4)

#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)

#define RING_CTX_TIMESTAMP(base)		_MMIO((base) + 0x3a8) /* gen8+ */

#define RING_PREDICATE_RESULT(base)		_MMIO((base) + 0x3b8)

#define RING_FORCE_TO_NONPRIV(base, i)		_MMIO(((base) + 0x4D0) + (i) * 4)

#define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)

#define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */

drivers/gpu/drm/i915/gt/intel_engine_user.c

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { 
	[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,

	[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,

	[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,

	/* TODO: Add COMPUTE_CLASS mapping once ABI is available */

	[COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,

};



static int engine_cmp(void *priv, const struct list_head *A,

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+11 −4
Original line number Diff line number Diff line
@@ -3433,10 +3433,17 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) 
		}

	}



	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {

		if (intel_engine_has_preemption(engine))

			engine->emit_bb_start = gen125_emit_bb_start;

		else

			engine->emit_bb_start = gen125_emit_bb_start_noarb;

	} else {

		if (intel_engine_has_preemption(engine))

			engine->emit_bb_start = gen8_emit_bb_start;

		else

			engine->emit_bb_start = gen8_emit_bb_start_noarb;

	}



	engine->busyness = execlists_engine_busyness;

}