Commit b058e399 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Enable SubVP on PSR panels if single stream 



Enable SubVP on PSR panels now that we have FW support

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9ba90d76

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -209,6 +209,7 @@ struct dc_color_caps { 
struct dc_dmub_caps {

	bool psr;

	bool mclk_sw;

	bool subvp_psr;

};



struct dc_caps {

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -944,6 +944,7 @@ void dcn32_init_hw(struct dc *dc) 
	if (dc->ctx->dmub_srv) {

		dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

		dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

		dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;

		dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;

	}

}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+2 −1
Original line number Diff line number Diff line
@@ -692,7 +692,8 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, 
		 *   to combine this with SubVP can cause issues with the scheduling).

		 * - Not TMZ surface

		 */

		if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && !dcn32_is_psr_capable(pipe) &&

		if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&

				(!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&

				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&

				(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||

				(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&