Commit b05dee52 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix not enter/exit PSR with latest driver/SBIOS 



Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1bd4653a

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+1 −1
Original line number Diff line number Diff line
@@ -1975,7 +1975,7 @@ bool dc_link_setup_psr(struct dc_link *link, 
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

		/*skip power down the single pipe since it blocks the cstate*/

		if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))

			psr_context->psr_level.bits.SKIP_SINGLE_OTG_DISABLE = true;

			psr_context->psr_level.bits.SKIP_SINGLE_OTG_DISABLE = false;

#endif



		/* SMU will perform additional powerdown sequence.

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+2 −1
Original line number Diff line number Diff line
@@ -417,9 +417,10 @@ static int dce112_set_clock( 


	bp->funcs->set_dce_clock(bp, &dce_clk_params);



	if (abm->funcs->is_dmcu_initialized(abm))

	if (abm->funcs->is_dmcu_initialized(abm) && clk_dce->dfs_bypass_disp_clk != actual_clock)

		dmcu->funcs->set_psr_wait_loop(dmcu,

				actual_clock / 1000 / 7);

	clk_dce->dfs_bypass_disp_clk = actual_clock;

	return actual_clock;

}

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

+4 −1
Original line number Diff line number Diff line
@@ -260,6 +260,8 @@ static void dce_psr_wait_loop( 
{

	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;

	if (cached_wait_loop_number == wait_loop_number)

		return;



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
@@ -500,7 +502,7 @@ static void dcn10_psr_wait_loop( 
{

	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;



	if (wait_loop_number != 0) {

	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
@@ -515,6 +517,7 @@ static void dcn10_psr_wait_loop( 
	/* notifyDMCUMsg */

	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

	}

}



static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number)

{