Commit b15bfd0d authored by Joshua Aberback's avatar Joshua Aberback Committed by Alex Deucher
Browse files

drm/amd/display: Revert HUBP blank behaviour for now 



[Why]
Commit "Blank HUBP during pixel data blank for DCN30 v2"
modifies HW behaviour during blank, which might have OS
dependencies. We need to assess the impact on amdgpu_dm
and only re-enable HUBP blanking when all necessary
changes are understood.

[How]
 - revert functional changes
 - leave architectural changes intact

Signed-off-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8edb9456

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

+2 −25
Original line number Diff line number Diff line
@@ -824,29 +824,6 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, 
		const struct tg_color *solid_color,

		int width, int height, int offset)

{

	struct stream_resource *stream_res = &pipe_ctx->stream_res;

	struct pipe_ctx *mpcc_pipe;



	if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {

		/* turning on DPG */

		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,

				color_depth, solid_color, width, height, 0);



		/* wait for the next frame when enabling DPG */

		if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg))

			dc->hwseq->funcs.wait_for_blank_complete(stream_res->opp);



		/* Blank HUBP to allow p-state during blank on all timings */

		pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);

		for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)

			mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);

	} else {

		/* turning off DPG */

		pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);

		for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)

			mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);



		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,

				color_depth, solid_color, width, height, 0);

	}

	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

			color_space, color_depth, solid_color, width, height, 0);

}

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

+1 −1
Original line number Diff line number Diff line
@@ -5558,7 +5558,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( 
		}

	}



	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {

	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {

		*DRAMClockChangeSupport = dm_dram_clock_change_vactive;

	} else if (((mode_lib->vba.SynchronizedVBlank == true || mode_lib->vba.TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {

		*DRAMClockChangeSupport = dm_dram_clock_change_vblank;