Commit b15cde19 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Add i2c speed arbitration for dc_i2c and hdcp_i2c 



[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.

[how]
Slow down the HW i2c speed when used by HW i2c.
This request: each acquired_i2c_engine setup the i2c speed needed
and sets the I2c engine for HDCP use at release_engine.

This covers SW using HW i2c engine and HDCP using HW i2c engine.
for dmcu using HW i2c engine, needs add similar logic in dmcu fw.

Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 54e8094a

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ struct dc_caps { 
	uint32_t max_planes;

	uint32_t max_downscale_ratio;

	uint32_t i2c_speed_in_khz;

	uint32_t i2c_speed_in_khz_hdcp;

	uint32_t dmdata_alloc_size;

	unsigned int max_cursor_size;

	unsigned int max_video_width;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

+7 −2
Original line number Diff line number Diff line
@@ -299,8 +299,12 @@ static bool setup_engine( 
	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/

	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);



	/*set SW requested I2c speed to default, if API calls in it will be override later*/

	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);



	if (dce_i2c_hw->setup_limit != 0)

		i2c_setup_limit = dce_i2c_hw->setup_limit;



	/* Program pin select */

	REG_UPDATE_6(DC_I2C_CONTROL,

		     DC_I2C_GO, 0,
@@ -339,8 +343,6 @@ static void release_engine( 
{

	bool safe_to_reset;



	/* Restore original HW engine speed */

	set_speed(dce_i2c_hw, dce_i2c_hw->default_speed);



	/* Reset HW engine */

	{
@@ -360,6 +362,9 @@ static void release_engine( 
	/* HW I2c engine - clock gating feature */

	if (!dce_i2c_hw->engine_keep_power_up_count)

		REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);



	/*for HW HDCP Ri polling failure w/a test*/

	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);

	/* Release I2C after reset, so HW or DMCU could use it */

	REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,

		DC_I2C_SW_USE_I2C_REG_REQ, 0);

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1071,6 +1071,7 @@ static bool dce100_resource_construct( 
	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.max_cursor_size = 128;

	dc->caps.dual_link_dvi = true;

	dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -1372,7 +1372,8 @@ static bool dce110_resource_construct( 
	pool->base.underlay_pipe_index = pool->base.pipe_count;

	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 150;

	dc->caps.i2c_speed_in_khz = 100;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.i2c_speed_in_khz_hdcp = 40;

	dc->caps.max_cursor_size = 128;

	dc->caps.is_apu = true;

	dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1240,6 +1240,7 @@ static bool dce112_resource_construct( 
	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 100;

	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

	dc->caps.max_cursor_size = 128;

	dc->caps.dual_link_dvi = true;

	dc->caps.extended_aux_timeout_support = false;