Commit b2d5025e authored by Sudeep Holla's avatar Sudeep Holla
Browse files

arm64: dts: fvp: Add information about L1 and L2 caches 

Add the information about L1 and L2 caches on FVP RevC platform.
Though the cache size is configurable through the model parameters,
having default values in the device tree helps to exercise and debug
any code utilising the cache information without the need of real
hardware.

Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com


Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 3bd7a021

arch/arm64/boot/dts/arm/fvp-base-revc.dts

+73 −0
Original line number Diff line number Diff line
@@ -47,48 +47,121 @@ cpu0: cpu@0 { 
			compatible = "arm,armv8";

			reg = <0x0 0x000>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu4: cpu@10000 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10000>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		cpu5: cpu@10100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10100>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		cpu6: cpu@10200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10200>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		cpu7: cpu@10300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10300>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		C0_L2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};



		C1_L2: l2-cache1 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};

	};