Commit b3ea0eaf authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/misc' into for-next/core 

* for-next/misc:
  arm64: mm: Drop 'const' from conditional arm64_dma_phys_limit definition
  arm64: clean up tools Makefile
  arm64: drop unused includes of <linux/personality.h>
  arm64: Do not defer reserve_crashkernel() for platforms with no DMA memory zones
  arm64: prevent instrumentation of bp hardening callbacks
  arm64: cpufeature: Remove cpu_has_fwb() check
  arm64: atomics: remove redundant static branch
  arm64: entry: Save some nops when CONFIG_ARM64_PSEUDO_NMI is not set
parents 563c4635 77009345

arch/arm64/include/asm/lse.h

+2 −4
Original line number Diff line number Diff line
@@ -17,12 +17,10 @@ 
#include <asm/cpucaps.h>



extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];

extern struct static_key_false arm64_const_caps_ready;



static inline bool system_uses_lse_atomics(void)

static __always_inline bool system_uses_lse_atomics(void)

{

	return (static_branch_likely(&arm64_const_caps_ready)) &&

		static_branch_likely(&cpu_hwcap_keys[ARM64_HAS_LSE_ATOMICS]);

	return static_branch_likely(&cpu_hwcap_keys[ARM64_HAS_LSE_ATOMICS]);

}



#define __lse_ll_sc_body(op, ...)					\

arch/arm64/include/asm/spectre.h

+2 −1
Original line number Diff line number Diff line
@@ -67,7 +67,8 @@ struct bp_hardening_data { 


DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);



static inline void arm64_apply_bp_hardening(void)

/* Called during entry so must be __always_inline */

static __always_inline void arm64_apply_bp_hardening(void)

{

	struct bp_hardening_data *d;

arch/arm64/kernel/cpufeature.c

+0 −9
Original line number Diff line number Diff line
@@ -1775,14 +1775,6 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 
		write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);

}



static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)

{

	u64 val = read_sysreg_s(SYS_CLIDR_EL1);



	/* Check that CLIDR_EL1.LOU{U,IS} are both 0 */

	WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val));

}



#ifdef CONFIG_ARM64_PAN

static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)

{
@@ -2144,7 +2136,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64MMFR2_FWB_SHIFT,

		.min_field_value = 1,

		.matches = has_cpuid_feature,

		.cpu_enable = cpu_has_fwb,

	},

	{

		.desc = "ARMv8.4 Translation Table Level",

arch/arm64/kernel/entry.S

+4 −0
Original line number Diff line number Diff line
@@ -300,6 +300,7 @@ alternative_else_nop_endif 
	str	w21, [sp, #S_SYSCALLNO]

	.endif



#ifdef CONFIG_ARM64_PSEUDO_NMI

	/* Save pmr */

alternative_if ARM64_HAS_IRQ_PRIO_MASKING

	mrs_s	x20, SYS_ICC_PMR_EL1
@@ -307,6 +308,7 @@ alternative_if ARM64_HAS_IRQ_PRIO_MASKING 
	mov	x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET

	msr_s	SYS_ICC_PMR_EL1, x20

alternative_else_nop_endif

#endif



	/* Re-enable tag checking (TCO set on exception entry) */

#ifdef CONFIG_ARM64_MTE
@@ -330,6 +332,7 @@ alternative_else_nop_endif 
	disable_daif

	.endif



#ifdef CONFIG_ARM64_PSEUDO_NMI

	/* Restore pmr */

alternative_if ARM64_HAS_IRQ_PRIO_MASKING

	ldr	x20, [sp, #S_PMR_SAVE]
@@ -339,6 +342,7 @@ alternative_if ARM64_HAS_IRQ_PRIO_MASKING 
	dsb	sy				// Ensure priority change is seen by redistributor

.L__skip_pmr_sync\@:

alternative_else_nop_endif

#endif



	ldp	x21, x22, [sp, #S_PC]		// load ELR, SPSR

arch/arm64/kernel/proton-pack.c

+6 −3
Original line number Diff line number Diff line
@@ -193,17 +193,20 @@ static void install_bp_hardening_cb(bp_hardening_cb_t fn) 
	__this_cpu_write(bp_hardening_data.slot, HYP_VECTOR_SPECTRE_DIRECT);

}



static void call_smc_arch_workaround_1(void)

/* Called during entry so must be noinstr */

static noinstr void call_smc_arch_workaround_1(void)

{

	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);

}



static void call_hvc_arch_workaround_1(void)

/* Called during entry so must be noinstr */

static noinstr void call_hvc_arch_workaround_1(void)

{

	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);

}



static void qcom_link_stack_sanitisation(void)

/* Called during entry so must be noinstr */

static noinstr void qcom_link_stack_sanitisation(void)

{

	u64 tmp;