Commit b49977a6 authored by Matthijs Kooijman's avatar Matthijs Kooijman Committed by Greg Kroah-Hartman
Browse files

staging: dwc2: toggle periodic debugging output separately 



This adds a config option USB_DWC2_DEBUG_PERIODIC that allows debugging
output be suppressed for periodic transfers. This helps when debugging
non-periodic transfers while there are also periodic transfers going on
(both to make the debug output less polluted and to prevent all CPU time
going to debug messages).

In addition, a debug message from dwc2_hcd_is_status_changed is removed
entirely, since it often floods the log regardless of periodic
transfers.

Signed-off-by: default avatarMatthijs Kooijman <matthijs@stdin.nl>
Cc: Paul Zimmerman <Paul.Zimmerman@synopsys.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 096e490a

drivers/staging/dwc2/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -39,4 +39,14 @@ config USB_DWC2_TRACK_MISSED_SOFS 
	  Say Y here to enable logging of missed SOF events to the dmesg log.

	  If in doubt, say N.



config USB_DWC2_DEBUG_PERIODIC

	bool "Enable Debugging Messages For Periodic Transfers"

	depends on USB_DWC2_DEBUG || USB_DWC2_VERBOSE

	default y

	help

	  Say N here to disable (verbose) debugging messages to be

	  logged for periodic transfers. This allows better debugging of

	  non-periodic transfers, but of course the debug logs will be

	  incomplete. Note that this also disables some debug messages

	  for which the transfer type cannot be deduced.

endif

drivers/staging/dwc2/core.c

+168 −98
Original line number Diff line number Diff line
@@ -717,6 +717,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 
		break;



	case USB_ENDPOINT_XFER_INT:

		if (dbg_perio())

			dev_vdbg(hsotg->dev, "intr\n");

		hcintmsk |= HCINTMSK_XFERCOMPL;

		hcintmsk |= HCINTMSK_NAK;
@@ -738,6 +739,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 
		break;



	case USB_ENDPOINT_XFER_ISOC:

		if (dbg_perio())

			dev_vdbg(hsotg->dev, "isoc\n");

		hcintmsk |= HCINTMSK_XFERCOMPL;

		hcintmsk |= HCINTMSK_FRMOVRUN;
@@ -754,6 +756,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 
	}



	writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);

}
@@ -767,9 +770,11 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 
	 * Interrupt is not required.

	 */

	if (hsotg->core_params->dma_desc_enable <= 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "desc DMA disabled\n");

		hcintmsk |= HCINTMSK_AHBERR;

	} else {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "desc DMA enabled\n");

		if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)

			hcintmsk |= HCINTMSK_XFERCOMPL;
@@ -777,6 +782,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 


	if (chan->error_state && !chan->do_split &&

	    chan->ep_type != USB_ENDPOINT_XFER_ISOC) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "setting ACK\n");

		hcintmsk |= HCINTMSK_ACK;

		if (chan->ep_is_in) {
@@ -787,6 +793,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 
	}



	writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);

}
@@ -796,9 +803,11 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 
	u32 intmsk;



	if (hsotg->core_params->dma_enable > 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA enabled\n");

		dwc2_hc_enable_dma_ints(hsotg, chan);

	} else {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA disabled\n");

		dwc2_hc_enable_slave_ints(hsotg, chan);

	}
@@ -807,12 +816,14 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 
	intmsk = readl(hsotg->regs + HAINTMSK);

	intmsk |= 1 << chan->hc_num;

	writel(intmsk, hsotg->regs + HAINTMSK);

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);



	/* Make sure host channel interrupts are enabled */

	intmsk = readl(hsotg->regs + GINTMSK);

	intmsk |= GINTSTS_HCHINT;

	writel(intmsk, hsotg->regs + GINTMSK);

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);

}
@@ -834,6 +845,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 
	u32 hcchar;

	u32 hcsplt = 0;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s()\n", __func__);



	/* Clear old interrupt conditions for this host channel */
@@ -857,7 +869,9 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 
	hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;

	hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;

	writel(hcchar, hsotg->regs + HCCHAR(hc_num));

	dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", hc_num, hcchar);

	if (dbg_hc(chan)) {

		dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",

			 hc_num, hcchar);



		dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, hc_num);

		dev_vdbg(hsotg->dev, "	 Dev Addr: %d\n",
@@ -866,7 +880,8 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 
		dev_vdbg(hsotg->dev, "	 Ep Num: %d\n",

			 hcchar >> HCCHAR_EPNUM_SHIFT &

			 HCCHAR_EPNUM_MASK >> HCCHAR_EPNUM_SHIFT);

	dev_vdbg(hsotg->dev, "	 Is In: %d\n", !!(hcchar & HCCHAR_EPDIR));

		dev_vdbg(hsotg->dev, "	 Is In: %d\n",

			 !!(hcchar & HCCHAR_EPDIR));

		dev_vdbg(hsotg->dev, "	 Is Low Speed: %d\n",

			 !!(hcchar & HCCHAR_LSPDDEV));

		dev_vdbg(hsotg->dev, "	 Ep Type: %d\n",
@@ -878,11 +893,15 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 
		dev_vdbg(hsotg->dev, "	 Multi Cnt: %d\n",

			 hcchar >> HCCHAR_MULTICNT_SHIFT &

			 HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);

	}



	/* Program the HCSPLT register for SPLITs */

	if (chan->do_split) {

		dev_vdbg(hsotg->dev, "Programming HC %d with split --> %s\n",

			 hc_num, chan->complete_split ? "CSPLIT" : "SSPLIT");

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev,

				 "Programming HC %d with split --> %s\n",

				 hc_num,

				 chan->complete_split ? "CSPLIT" : "SSPLIT");

		if (chan->complete_split)

			hcsplt |= HCSPLT_COMPSPLT;

		hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
@@ -891,16 +910,23 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 
			  HCSPLT_HUBADDR_MASK;

		hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &

			  HCSPLT_PRTADDR_MASK;

		if (dbg_hc(chan)) {

			dev_vdbg(hsotg->dev, "	  comp split %d\n",

				 chan->complete_split);

		dev_vdbg(hsotg->dev, "	  xact pos %d\n", chan->xact_pos);

		dev_vdbg(hsotg->dev, "	  hub addr %d\n", chan->hub_addr);

		dev_vdbg(hsotg->dev, "	  hub port %d\n", chan->hub_port);

		dev_vdbg(hsotg->dev, "	  is_in %d\n", chan->ep_is_in);

			dev_vdbg(hsotg->dev, "	  xact pos %d\n",

				 chan->xact_pos);

			dev_vdbg(hsotg->dev, "	  hub addr %d\n",

				 chan->hub_addr);

			dev_vdbg(hsotg->dev, "	  hub port %d\n",

				 chan->hub_port);

			dev_vdbg(hsotg->dev, "	  is_in %d\n",

				 chan->ep_is_in);

			dev_vdbg(hsotg->dev, "	  Max Pkt %d\n",

				 hcchar >> HCCHAR_MPS_SHIFT &

				 HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);

		dev_vdbg(hsotg->dev, "	  xferlen %d\n", chan->xfer_len);

			dev_vdbg(hsotg->dev, "	  xferlen %d\n",

				 chan->xfer_len);

		}

	}



	writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
@@ -939,6 +965,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 
{

	u32 nptxsts, hptxsts, hcchar;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s()\n", __func__);

	if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)

		dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
@@ -1003,14 +1030,17 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 
	/* No need to set the bit in DDMA for disabling the channel */

	/* TODO check it everywhere channel is disabled */

	if (hsotg->core_params->dma_desc_enable <= 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "desc DMA disabled\n");

		hcchar |= HCCHAR_CHENA;

	} else {

		if (dbg_hc(chan))

			dev_dbg(hsotg->dev, "desc DMA enabled\n");

	}

	hcchar |= HCCHAR_CHDIS;



	if (hsotg->core_params->dma_enable <= 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA not enabled\n");

		hcchar |= HCCHAR_CHENA;
@@ -1024,15 +1054,18 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 
				hcchar &= ~HCCHAR_CHENA;

			}

		} else {

			if (dbg_perio())

				dev_vdbg(hsotg->dev, "isoc/intr\n");

			hptxsts = readl(hsotg->regs + HPTXSTS);

			if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||

			    hsotg->queuing_high_bandwidth) {

				if (dbg_perio())

					dev_vdbg(hsotg->dev, "Disabling channel\n");

				hcchar &= ~HCCHAR_CHENA;

			}

		}

	} else {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA enabled\n");

	}
@@ -1040,19 +1073,28 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 
	chan->halt_status = halt_status;



	if (hcchar & HCCHAR_CHENA) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "Channel enabled\n");

		chan->halt_pending = 1;

		chan->halt_on_queue = 0;

	} else {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "Channel disabled\n");

		chan->halt_on_queue = 1;

	}



	dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, chan->hc_num);

	dev_vdbg(hsotg->dev, "	 hcchar: 0x%08x\n", hcchar);

	dev_vdbg(hsotg->dev, "	 halt_pending: %d\n", chan->halt_pending);

	dev_vdbg(hsotg->dev, "	 halt_on_queue: %d\n", chan->halt_on_queue);

	dev_vdbg(hsotg->dev, "	 halt_status: %d\n", chan->halt_status);

	if (dbg_hc(chan)) {

		dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,

			 chan->hc_num);

		dev_vdbg(hsotg->dev, "	 hcchar: 0x%08x\n",

			 hcchar);

		dev_vdbg(hsotg->dev, "	 halt_pending: %d\n",

			 chan->halt_pending);

		dev_vdbg(hsotg->dev, "	 halt_on_queue: %d\n",

			 chan->halt_on_queue);

		dev_vdbg(hsotg->dev, "	 halt_status: %d\n",

			 chan->halt_status);

	}

}



/**
@@ -1153,6 +1195,7 @@ static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 
	u32 __iomem *data_fifo;

	u32 *data_buf = (u32 *)chan->xfer_buf;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s()\n", __func__);



	data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
@@ -1224,21 +1267,25 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
	u32 hctsiz = 0;

	u16 num_packets;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s()\n", __func__);



	if (chan->do_ping) {

		if (hsotg->core_params->dma_enable <= 0) {

			if (dbg_hc(chan))

				dev_vdbg(hsotg->dev, "ping, no DMA\n");

			dwc2_hc_do_ping(hsotg, chan);

			chan->xfer_started = 1;

			return;

		} else {

			if (dbg_hc(chan))

				dev_vdbg(hsotg->dev, "ping, DMA\n");

			hctsiz |= TSIZ_DOPNG;

		}

	}



	if (chan->do_split) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "split\n");

		num_packets = 1;
@@ -1256,6 +1303,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
		hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &

			  TSIZ_XFERSIZE_MASK;

	} else {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "no split\n");

		/*

		 * Ensure that the transfer length and packet count will fit
@@ -1323,10 +1371,12 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
	hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &

		  TSIZ_SC_MC_PID_MASK;

	writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));

	if (dbg_hc(chan)) {

		dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",

			 hctsiz, chan->hc_num);



	dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, chan->hc_num);

		dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,

			 chan->hc_num);

		dev_vdbg(hsotg->dev, "	 Xfer Size: %d\n",

			 hctsiz >> TSIZ_XFERSIZE_SHIFT &

			 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
@@ -1336,17 +1386,20 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
		dev_vdbg(hsotg->dev, "	 Start PID: %d\n",

			 hctsiz >> TSIZ_SC_MC_PID_SHIFT &

			 TSIZ_SC_MC_PID_MASK >> TSIZ_SC_MC_PID_SHIFT);

	}



	if (hsotg->core_params->dma_enable > 0) {

		dma_addr_t dma_addr;



		if (chan->align_buf) {

			if (dbg_hc(chan))

				dev_vdbg(hsotg->dev, "align_buf\n");

			dma_addr = chan->align_buf;

		} else {

			dma_addr = chan->xfer_dma;

		}

		writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",

				 (unsigned long)dma_addr, chan->hc_num);

	}
@@ -1374,11 +1427,13 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
	hcchar |= HCCHAR_CHENA;

	hcchar &= ~HCCHAR_CHDIS;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "	 Multi Cnt: %d\n",

			 hcchar >> HCCHAR_MULTICNT_SHIFT &

			 HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);



	writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,

			 chan->hc_num);
@@ -1428,9 +1483,13 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 
	/* Non-zero only for high-speed interrupt endpoints */

	hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;



	dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, chan->hc_num);

	dev_vdbg(hsotg->dev, "	 Start PID: %d\n", chan->data_pid_start);

	if (dbg_hc(chan)) {

		dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,

			 chan->hc_num);

		dev_vdbg(hsotg->dev, "	 Start PID: %d\n",

			 chan->data_pid_start);

		dev_vdbg(hsotg->dev, "	 NTD: %d\n", chan->ntd - 1);

	}



	writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
@@ -1439,7 +1498,9 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 
	/* Always start from first descriptor */

	hc_dma &= ~HCDMA_CTD_MASK;

	writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));

	dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", hc_dma, chan->hc_num);

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",

			 hc_dma, chan->hc_num);



	hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));

	hcchar &= ~HCCHAR_MULTICNT_MASK;
@@ -1455,11 +1516,13 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 
	hcchar |= HCCHAR_CHENA;

	hcchar &= ~HCCHAR_CHDIS;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "	 Multi Cnt: %d\n",

			 hcchar >> HCCHAR_MULTICNT_SHIFT &

			 HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);



	writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,

			 chan->hc_num);
@@ -1490,7 +1553,9 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 
int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,

			      struct dwc2_host_chan *chan)

{

	dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, chan->hc_num);

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,

			 chan->hc_num);



	if (chan->do_split)

		/* SPLITs always queue just once per channel */
@@ -1518,7 +1583,9 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 
		dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);

		hcchar |= HCCHAR_CHENA;

		hcchar &= ~HCCHAR_CHDIS;

		dev_vdbg(hsotg->dev, "	 IN xfer: hcchar = 0x%08x\n", hcchar);

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "	 IN xfer: hcchar = 0x%08x\n",

				 hcchar);

		writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));

		chan->requests++;

		return 1;
@@ -1559,7 +1626,10 @@ void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 
	u32 hcchar;

	u32 hctsiz;



	dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, chan->hc_num);

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,

			 chan->hc_num);





	hctsiz = TSIZ_DOPNG;

	hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;

drivers/staging/dwc2/hcd.c

+37 −26
Original line number Diff line number Diff line
@@ -725,6 +725,7 @@ static void dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, 
	struct dwc2_qtd *qtd;

	void *bufptr = NULL;



	if (dbg_qh(qh))

		dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);



	if (list_empty(&qh->qtd_list)) {
@@ -1001,6 +1002,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 
	int no_fifo_space = 0;

	u32 qspcavail;



	if (dbg_perio())

		dev_vdbg(hsotg->dev, "Queue periodic transactions\n");



	tx_status = readl(hsotg->regs + HPTXSTS);
@@ -1008,10 +1010,13 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 
		    TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;

	fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &

		    TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;



	if (dbg_perio()) {

		dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",

			 qspcavail);

		dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",

			 fspcavail);

	}



	qh_ptr = hsotg->periodic_sched_assigned.next;

	while (qh_ptr != &hsotg->periodic_sched_assigned) {
@@ -1078,12 +1083,14 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 
			    TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;

		fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &

			    TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;

		if (dbg_perio()) {

			dev_vdbg(hsotg->dev,

				 "  P Tx Req Queue Space Avail (after queue): %d\n",

				 qspcavail);

			dev_vdbg(hsotg->dev,

				 "  P Tx FIFO Space Avail (after queue): %d\n",

				 fspcavail);

		}



		if (!list_empty(&hsotg->periodic_sched_assigned) ||

		    no_queue_space || no_fifo_space) {
@@ -1722,8 +1729,6 @@ static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 
{

	int retval;



	dev_vdbg(hsotg->dev, "%s()\n", __func__);



	if (port != 1)

		return -EINVAL;
@@ -1787,6 +1792,9 @@ static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 
				      struct dwc2_hcd_urb *urb, u8 dev_addr,

				      u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)

{

	if (dbg_perio() ||

	    ep_type == USB_ENDPOINT_XFER_BULK ||

	    ep_type == USB_ENDPOINT_XFER_CONTROL)

		dev_vdbg(hsotg->dev,

			 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",

			 dev_addr, ep_num, ep_dir, ep_type, mps);
@@ -2098,6 +2106,7 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, void *context, 


	urb->actual_length = dwc2_hcd_urb_get_actual_length(dwc2_urb);



	if (dbg_urb(urb))

		dev_vdbg(hsotg->dev,

			 "%s: urb %p device %d ep %d-%s status %d actual %d\n",

			 __func__, urb, usb_pipedevice(urb->pipe),
@@ -2105,7 +2114,7 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, void *context, 
			 usb_pipein(urb->pipe) ? "IN" : "OUT", status,

			 urb->actual_length);



	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {

	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {

		for (i = 0; i < urb->number_of_packets; i++)

			dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",

				 i, urb->iso_frame_desc[i].status);
@@ -2335,8 +2344,10 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 
	void *buf;

	unsigned long flags;



	if (dbg_urb(urb)) {

		dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");

		dwc2_dump_urb_info(hcd, urb, "urb_enqueue");

	}



	if (ep == NULL)

		return -EINVAL;

drivers/staging/dwc2/hcd.h

+27 −0
Original line number Diff line number Diff line
@@ -496,6 +496,33 @@ extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 
	((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \

	 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)



#ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC

static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }

static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }

static inline bool dbg_urb(struct urb *urb) { return true; }

static inline bool dbg_perio(void) { return true; }

#else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */

static inline bool dbg_hc(struct dwc2_host_chan *hc)

{

	return hc->ep_type == USB_ENDPOINT_XFER_BULK ||

	       hc->ep_type == USB_ENDPOINT_XFER_CONTROL;

}



static inline bool dbg_qh(struct dwc2_qh *qh)

{

	return qh->ep_type == USB_ENDPOINT_XFER_BULK ||

	       qh->ep_type == USB_ENDPOINT_XFER_CONTROL;

}



static inline bool dbg_urb(struct urb *urb)

{

	return usb_pipetype(urb->pipe) == PIPE_BULK ||

	       usb_pipetype(urb->pipe) == PIPE_CONTROL;

}



static inline bool dbg_perio(void) { return false; }

#endif



/* High bandwidth multiplier as encoded in highspeed endpoint descriptors */

#define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))

drivers/staging/dwc2/hcd_intr.c

+72 −45
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 
	u32 grxsts, chnum, bcnt, dpid, pktsts;

	struct dwc2_host_chan *chan;



	if (dbg_perio())

		dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");



	grxsts = readl(hsotg->regs + GRXSTSP);
@@ -179,6 +180,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 
	pktsts = grxsts & GRXSTS_PKTSTS_MASK;



	/* Packet Status */

	if (dbg_perio()) {

		dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);

		dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);

		dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
@@ -186,6 +188,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 
		dev_vdbg(hsotg->dev, "    PStatus = %d\n",

			 pktsts >> GRXSTS_PKTSTS_SHIFT &

			 GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT);

	}



	switch (pktsts) {

	case GRXSTS_PKTSTS_HCHIN:
@@ -230,6 +233,7 @@ static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 
 */

static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)

{

	if (dbg_perio())

		dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");

	dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);

}
@@ -646,7 +650,9 @@ static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 
	int continue_split = 0;

	struct dwc2_qtd *qtd;



	dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__, hsotg, qh, free_qtd);

	if (dbg_qh(qh))

		dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,

			 hsotg, qh, free_qtd);



	if (list_empty(&qh->qtd_list)) {

		dev_dbg(hsotg->dev, "## QTD list empty ##\n");
@@ -695,6 +701,7 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg, 
	u32 haintmsk;

	int free_qtd = 0;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",

			 __func__, chan->hc_num, halt_status);
@@ -791,9 +798,11 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, 
			      struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,

			      enum dwc2_halt_status halt_status)

{

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "%s()\n", __func__);



	if (hsotg->core_params->dma_enable > 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA enabled\n");

		dwc2_release_channel(hsotg, chan, qtd, halt_status);

		return;
@@ -977,8 +986,10 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, 
	enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;

	int urb_xfer_done;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev,

		 "--Host Channel %d Interrupt: Transfer Complete--\n", chnum);

			 "--Host Channel %d Interrupt: Transfer Complete--\n",

			 chnum);



	if (hsotg->core_params->dma_desc_enable > 0) {

		dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
@@ -1079,6 +1090,7 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, 
					    halt_status);

		break;

	case USB_ENDPOINT_XFER_ISOC:

		if (dbg_perio())

			dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");

		if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)

			halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
@@ -1197,6 +1209,7 @@ static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, 
			     struct dwc2_host_chan *chan, int chnum,

			     struct dwc2_qtd *qtd)

{

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",

			 chnum);
@@ -1274,6 +1287,7 @@ static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, 
{

	struct dwc2_hcd_iso_packet_desc *frame_desc;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",

			 chnum);
@@ -1350,6 +1364,7 @@ static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, 
			      struct dwc2_host_chan *chan, int chnum,

			      struct dwc2_qtd *qtd)

{

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",

			 chnum);
@@ -1630,6 +1645,7 @@ static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, 
{

	enum dwc2_halt_status halt_status;



	if (dbg_hc(chan))

		dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",

			chnum);
@@ -1747,8 +1763,10 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, 
	u32 hcintmsk;

	int out_nak_enh = 0;



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev,

		 "--Host Channel %d Interrupt: DMA Channel Halted--\n", chnum);

			 "--Host Channel %d Interrupt: DMA Channel Halted--\n",

			 chnum);



	/*

	 * For core with OUT NAK enhancement, the flow for high-speed
@@ -1900,6 +1918,7 @@ static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, 
				struct dwc2_host_chan *chan, int chnum,

				struct dwc2_qtd *qtd)

{

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",

			 chnum);
@@ -1919,15 +1938,19 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) 
	struct dwc2_host_chan *chan;

	u32 hcint, hcintmsk;



	dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", chnum);

	chan = hsotg->hc_ptr_array[chnum];



	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",

			 chnum);



	hcint = readl(hsotg->regs + HCINT(chnum));

	hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));

	if (dbg_hc(chan))

		dev_vdbg(hsotg->dev,

			 "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",

			 hcint, hcintmsk, hcint & hcintmsk);



	chan = hsotg->hc_ptr_array[chnum];

	if (!chan) {

		dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");

		writel(hcint, hsotg->regs + HCINT(chnum));
@@ -2026,10 +2049,12 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) 
	u32 haint;

	int i;



	haint = readl(hsotg->regs + HAINT);

	if (dbg_perio()) {

		dev_vdbg(hsotg->dev, "%s()\n", __func__);



	haint = readl(hsotg->regs + HAINT);

		dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);

	}



	for (i = 0; i < hsotg->core_params->host_channels; i++) {

		if (haint & (1 << i))
@@ -2040,7 +2065,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) 
/* This function handles interrupts for the HCD */

int dwc2_hcd_intr(struct dwc2_hsotg *hsotg)

{

	u32 gintsts;

	u32 gintsts, dbg_gintsts;

	int retval = 0;



	if (dwc2_check_core_status(hsotg) < 0) {
@@ -2060,10 +2085,16 @@ int dwc2_hcd_intr(struct dwc2_hsotg *hsotg) 


		retval = 1;



		dbg_gintsts = gintsts;

#ifndef DEBUG_SOF

		/* Don't print debug message in the interrupt handler on SOF */

		if (gintsts != GINTSTS_SOF)

		dbg_gintsts &= ~GINTSTS_SOF;

#endif

		if (!dbg_perio())

			dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |

					 GINTSTS_PTXFEMP);



		/* Only print if there are any non-suppressed interrupts left */

		if (dbg_gintsts)

			dev_vdbg(hsotg->dev,

				 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",

				 gintsts);
@@ -2084,18 +2115,14 @@ int dwc2_hcd_intr(struct dwc2_hsotg *hsotg) 
		if (gintsts & GINTSTS_PTXFEMP)

			dwc2_perio_tx_fifo_empty_intr(hsotg);



#ifndef DEBUG_SOF

		if (gintsts != GINTSTS_SOF) {

#endif

		if (dbg_gintsts) {

			dev_vdbg(hsotg->dev,

				 "DWC OTG HCD Finished Servicing Interrupts\n");

			dev_vdbg(hsotg->dev,

				 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",

				 readl(hsotg->regs + GINTSTS),

				 readl(hsotg->regs + GINTMSK));

#ifndef DEBUG_SOF

		}

#endif

	}



	spin_unlock(&hsotg->lock);