Commit b4da7fc3 authored by Rene Sapiens's avatar Rene Sapiens Committed by Omar Ramirez Luna
Browse files

staging: tidspbridge: set1 remove hungarian from structs 



hungarian notation will be removed from the elements inside
structures, the next varibles will be renamed:

dw_api_reg_base         api_reg_base
dw_brd_state            brd_state
dw_chnl_buf_size        chnl_buf_size
dw_chnl_offset          chnl_offset
dw_cmd                  cmd
dw_core_pm_base         core_pm_base
dw_dsp_base             dsp_base
dw_dsp_base_va          dsp_base_va
dw_dsp_bufs             dsp_bufs
dw_dsp_buf_size         dsp_buf_size
dw_dsp_clk_m2_base      dsp_clk_m2_base
dw_dsp_ext_base_addr    dsp_ext_base_addr
dw_dsp_phys_addr_offset dsp_phys_addr_offset
dw_dsp_start_add        dsp_start_add
dw_err_mask             err_mask
dw_gpp_base_pa          gpp_base_pa
dw_api_clk_base         api_clk_base
dw_api_reg_base         api_reg_base
dw_arg                  arg
dw_arg1                 arg1
dw_arg2                 arg2
dw_chnl_buf_size        chnl_buf_size

Signed-off-by: default avatarRene Sapiens <rene.sapiens@ti.com>
Signed-off-by: default avatarArmando Uribe <x0095078@ti.com>
Signed-off-by: default avatarOmar Ramirez Luna <omar.ramirez@ti.com>
parent 92d02930

drivers/staging/tidspbridge/core/_tiomap.h

+7 −7
Original line number Diff line number Diff line
@@ -320,22 +320,22 @@ static const struct bpwr_clk_t bpwr_clks[] = { 
/* This Bridge driver's device context: */

struct bridge_dev_context {

	struct dev_object *hdev_obj;	/* Handle to Bridge device object. */

	u32 dw_dsp_base_addr;	/* Arm's API to DSP virt base addr */

	u32 dsp_base_addr;	/* Arm's API to DSP virt base addr */

	/*

	 * DSP External memory prog address as seen virtually by the OS on

	 * the host side.

	 */

	u32 dw_dsp_ext_base_addr;	/* See the comment above */

	u32 dw_api_reg_base;	/* API mem map'd registers */

	u32 dsp_ext_base_addr;	/* See the comment above */

	u32 api_reg_base;	/* API mem map'd registers */

	void __iomem *dw_dsp_mmu_base;	/* DSP MMU Mapped registers */

	u32 dw_api_clk_base;	/* CLK Registers */

	u32 dw_dsp_clk_m2_base;	/* DSP Clock Module m2 */

	u32 api_clk_base;	/* CLK Registers */

	u32 dsp_clk_m2_base;	/* DSP Clock Module m2 */

	u32 dw_public_rhea;	/* Pub Rhea */

	u32 dw_int_addr;	/* MB INTR reg */

	u32 dw_tc_endianism;	/* TC Endianism register */

	u32 dw_test_base;	/* DSP MMU Mapped registers */

	u32 dw_self_loop;	/* Pointer to the selfloop */

	u32 dw_dsp_start_add;	/* API Boot vector */

	u32 dsp_start_add;	/* API Boot vector */

	u32 dw_internal_size;	/* Internal memory size */



	struct omap_mbox *mbox;		/* Mail box handle */
@@ -348,7 +348,7 @@ struct bridge_dev_context { 
	 */

	/* DMMU TLB entries */

	struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];

	u32 dw_brd_state;       /* Last known board state. */

	u32 brd_state;       /* Last known board state. */



	/* TC Settings */

	bool tc_word_swap_on;	/* Traffic Controller Word Swap */

drivers/staging/tidspbridge/core/chnl_sm.c

+3 −3
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *host_buf, 
	chnl_packet_obj->byte_size = byte_size;

	chnl_packet_obj->buf_size = buf_size;

	/* Only valid for output channel */

	chnl_packet_obj->dw_arg = dw_arg;

	chnl_packet_obj->arg = dw_arg;

	chnl_packet_obj->status = (is_eos ? CHNL_IOCSTATEOS :

			CHNL_IOCSTATCOMPLETE);

	list_add_tail(&chnl_packet_obj->link, &pchnl->pio_requests);
@@ -607,7 +607,7 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, 
		ioc.pbuf = chnl_packet_obj->host_user_buf;

		ioc.byte_size = chnl_packet_obj->byte_size;

		ioc.buf_size = chnl_packet_obj->buf_size;

		ioc.dw_arg = chnl_packet_obj->dw_arg;

		ioc.arg = chnl_packet_obj->arg;

		ioc.status |= chnl_packet_obj->status;

		/* Place the used chirp on the free list: */

		list_add_tail(&chnl_packet_obj->link,
@@ -615,7 +615,7 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, 
	} else {

		ioc.pbuf = NULL;

		ioc.byte_size = 0;

		ioc.dw_arg = 0;

		ioc.arg = 0;

		ioc.buf_size = 0;

	}

	/* Ensure invariant: If any IOC's are queued for this channel... */

drivers/staging/tidspbridge/core/io_sm.c

+19 −19
Original line number Diff line number Diff line
@@ -1113,7 +1113,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, 
						pio_mgr->input, bytes);

				pchnl->bytes_moved += bytes;

				chnl_packet_obj->byte_size = bytes;

				chnl_packet_obj->dw_arg = dw_arg;

				chnl_packet_obj->arg = dw_arg;

				chnl_packet_obj->status = CHNL_IOCSTATCOMPLETE;



				if (bytes == 0) {
@@ -1200,14 +1200,14 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr) 
	msg_input = pio_mgr->msg_input;

	for (i = 0; i < num_msgs; i++) {

		/* Read the next message */

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.dw_cmd);

		msg.msg.dw_cmd =

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.cmd);

		msg.msg.cmd =

			read_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr);

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.dw_arg1);

		msg.msg.dw_arg1 =

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.arg1);

		msg.msg.arg1 =

			read_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr);

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.dw_arg2);

		msg.msg.dw_arg2 =

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.arg2);

		msg.msg.arg2 =

			read_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr);

		addr = (u32) &(((struct msg_dspmsg *)msg_input)->msgq_id);

		msg.msgq_id =
@@ -1215,9 +1215,9 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr) 
		msg_input += sizeof(struct msg_dspmsg);



		/* Determine which queue to put the message in */

		dev_dbg(bridge,	"input msg: dw_cmd=0x%x dw_arg1=0x%x "

				"dw_arg2=0x%x msgq_id=0x%x\n", msg.msg.dw_cmd,

				msg.msg.dw_arg1, msg.msg.dw_arg2, msg.msgq_id);

		dev_dbg(bridge,	"input msg: cmd=0x%x arg1=0x%x "

				"arg2=0x%x msgq_id=0x%x\n", msg.msg.cmd,

				msg.msg.arg1, msg.msg.arg2, msg.msgq_id);

		/*

		 * Interrupt may occur before shared memory and message

		 * input locations have been set up. If all nodes were
@@ -1228,14 +1228,14 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr) 
			if (msg.msgq_id != msg_queue_obj->msgq_id)

				continue;

			/* Found it */

			if (msg.msg.dw_cmd == RMS_EXITACK) {

			if (msg.msg.cmd == RMS_EXITACK) {

				/*

				 * Call the node exit notification.

				 * The exit message does not get

				 * queued.

				 */

				(*hmsg_mgr->on_exit)(msg_queue_obj->arg,

						msg.msg.dw_arg1);

						msg.msg.arg1);

				break;

			}

			/*
@@ -1367,7 +1367,7 @@ static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, 
					chnl_packet_obj->byte_size);

	pchnl->bytes_moved += chnl_packet_obj->byte_size;

	/* Write all 32 bits of arg */

	sm->arg = chnl_packet_obj->dw_arg;

	sm->arg = chnl_packet_obj->arg;

#if _CHNL_WORDSIZE == 2

	/* Access can be different SM access word size (e.g. 16/32 bit words) */

	sm->output_id = (u16) chnl_id;
@@ -1430,16 +1430,16 @@ static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr) 
		addr = (u32) &msg_output->msgq_id;

		write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);



		val = (pmsg->msg_data).msg.dw_cmd;

		addr = (u32) &msg_output->msg.dw_cmd;

		val = (pmsg->msg_data).msg.cmd;

		addr = (u32) &msg_output->msg.cmd;

		write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);



		val = (pmsg->msg_data).msg.dw_arg1;

		addr = (u32) &msg_output->msg.dw_arg1;

		val = (pmsg->msg_data).msg.arg1;

		addr = (u32) &msg_output->msg.arg1;

		write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);



		val = (pmsg->msg_data).msg.dw_arg2;

		addr = (u32) &msg_output->msg.dw_arg2;

		val = (pmsg->msg_data).msg.arg2;

		addr = (u32) &msg_output->msg.arg2;

		write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);



		msg_output++;

drivers/staging/tidspbridge/core/tiomap3430.c

+25 −25
Original line number Diff line number Diff line
@@ -229,8 +229,8 @@ static struct notifier_block dsp_mbox_notifier = { 


static inline void flush_all(struct bridge_dev_context *dev_context)

{

	if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||

	    dev_context->dw_brd_state == BRD_HIBERNATION)

	if (dev_context->brd_state == BRD_DSP_HIBERNATION ||

	    dev_context->brd_state == BRD_HIBERNATION)

		wake_dsp(dev_context, NULL);



	hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base);
@@ -306,7 +306,7 @@ static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt) 
	dsp_clk_enable(DSP_CLK_IVA2);



	/* set the device state to IDLE */

	dev_context->dw_brd_state = BRD_IDLE;

	dev_context->brd_state = BRD_IDLE;



	return 0;

}
@@ -323,16 +323,16 @@ static int bridge_brd_read(struct bridge_dev_context *dev_ctxt, 
	int status = 0;

	struct bridge_dev_context *dev_context = dev_ctxt;

	u32 offset;

	u32 dsp_base_addr = dev_ctxt->dw_dsp_base_addr;

	u32 dsp_base_addr = dev_ctxt->dsp_base_addr;



	if (dsp_addr < dev_context->dw_dsp_start_add) {

	if (dsp_addr < dev_context->dsp_start_add) {

		status = -EPERM;

		return status;

	}

	/* change here to account for the 3 bands of the DSP internal memory */

	if ((dsp_addr - dev_context->dw_dsp_start_add) <

	if ((dsp_addr - dev_context->dsp_start_add) <

	    dev_context->dw_internal_size) {

		offset = dsp_addr - dev_context->dw_dsp_start_add;

		offset = dsp_addr - dev_context->dsp_start_add;

	} else {

		status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,

					   ul_num_bytes, mem_type);
@@ -354,7 +354,7 @@ static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt, 
	int status = 0;

	struct bridge_dev_context *dev_context = dev_ctxt;



	dev_context->dw_brd_state = brd_state;

	dev_context->brd_state = brd_state;

	return status;

}
@@ -616,10 +616,10 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, 
			__raw_writel(0XCAFECAFE, dw_sync_addr);



			/* update board state */

			dev_context->dw_brd_state = BRD_RUNNING;

			dev_context->brd_state = BRD_RUNNING;

			/* (void)chnlsm_enable_interrupt(dev_context); */

		} else {

			dev_context->dw_brd_state = BRD_UNKNOWN;

			dev_context->brd_state = BRD_UNKNOWN;

		}

	}

	return status;
@@ -642,7 +642,7 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) 
	struct omap_dsp_platform_data *pdata =

		omap_dspbridge_dev->dev.platform_data;



	if (dev_context->dw_brd_state == BRD_STOPPED)

	if (dev_context->brd_state == BRD_STOPPED)

		return status;



	/* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
@@ -667,10 +667,10 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) 
	udelay(10);

	/* Release the Ext Base virtual Address as the next DSP Program

	 * may have a different load address */

	if (dev_context->dw_dsp_ext_base_addr)

		dev_context->dw_dsp_ext_base_addr = 0;

	if (dev_context->dsp_ext_base_addr)

		dev_context->dsp_ext_base_addr = 0;



	dev_context->dw_brd_state = BRD_STOPPED;	/* update board state */

	dev_context->brd_state = BRD_STOPPED;	/* update board state */



	dsp_wdt_enable(false);
@@ -706,7 +706,7 @@ static int bridge_brd_status(struct bridge_dev_context *dev_ctxt, 
				    int *board_state)

{

	struct bridge_dev_context *dev_context = dev_ctxt;

	*board_state = dev_context->dw_brd_state;

	*board_state = dev_context->brd_state;

	return 0;

}
@@ -721,11 +721,11 @@ static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, 
	int status = 0;

	struct bridge_dev_context *dev_context = dev_ctxt;



	if (dsp_addr < dev_context->dw_dsp_start_add) {

	if (dsp_addr < dev_context->dsp_start_add) {

		status = -EPERM;

		return status;

	}

	if ((dsp_addr - dev_context->dw_dsp_start_add) <

	if ((dsp_addr - dev_context->dsp_start_add) <

	    dev_context->dw_internal_size) {

		status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,

					ul_num_bytes, mem_type);
@@ -764,7 +764,7 @@ static int bridge_dev_create(struct bridge_dev_context 
		goto func_end;

	}



	dev_context->dw_dsp_start_add = (u32) OMAP_GEM_BASE;

	dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;

	dev_context->dw_self_loop = (u32) NULL;

	dev_context->dsp_per_clks = 0;

	dev_context->dw_internal_size = OMAP_DSP_SIZE;
@@ -774,14 +774,14 @@ static int bridge_dev_create(struct bridge_dev_context 
		dev_context->atlb_entry[entry_ndx].ul_gpp_pa =

		    dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;

	}

	dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)

	dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)

								 (config_param->

								  dw_mem_base

								  [3]),

								 config_param->

								 dw_mem_length

								 [3]);

	if (!dev_context->dw_dsp_base_addr)

	if (!dev_context->dsp_base_addr)

		status = -EPERM;



	pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
@@ -874,7 +874,7 @@ static int bridge_dev_create(struct bridge_dev_context 
	if (!status) {

		dev_context->hdev_obj = hdev_obj;

		/* Store current board state. */

		dev_context->dw_brd_state = BRD_UNKNOWN;

		dev_context->brd_state = BRD_UNKNOWN;

		dev_context->resources = resources;

		dsp_clk_enable(DSP_CLK_IVA2);

		bridge_brd_stop(dev_context);
@@ -1032,8 +1032,8 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt) 
			iounmap(host_res->dw_per_base);

		if (host_res->dw_per_pm_base)

			iounmap((void *)host_res->dw_per_pm_base);

		if (host_res->dw_core_pm_base)

			iounmap((void *)host_res->dw_core_pm_base);

		if (host_res->core_pm_base)

			iounmap((void *)host_res->core_pm_base);



		host_res->dw_mem_base[0] = (u32) NULL;

		host_res->dw_mem_base[2] = (u32) NULL;
@@ -1070,7 +1070,7 @@ static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt, 
		status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,

					   copy_bytes, mem_type);

		if (!status) {

			if (dest_addr < (dev_context->dw_dsp_start_add +

			if (dest_addr < (dev_context->dsp_start_add +

					 dev_context->dw_internal_size)) {

				/* Write to Internal memory */

				status = write_dsp_data(dev_ctxt, host_buf,
@@ -1104,7 +1104,7 @@ static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt, 
	while (ul_remain_bytes > 0 && !status) {

		ul_bytes =

		    ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;

		if (dsp_addr < (dev_context->dw_dsp_start_add +

		if (dsp_addr < (dev_context->dsp_start_add +

				 dev_context->dw_internal_size)) {

			status =

			    write_dsp_data(dev_ctxt, host_buff, dsp_addr,

drivers/staging/tidspbridge/core/tiomap3430_pwr.c

+19 −19
Original line number Diff line number Diff line
@@ -118,7 +118,7 @@ int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context) 


		if (!status) {

			/* Update the Bridger Driver state */

			dev_context->dw_brd_state = BRD_DSP_HIBERNATION;

			dev_context->brd_state = BRD_DSP_HIBERNATION;

#ifdef CONFIG_TIDSPBRIDGE_DVFS

			status =

			    dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
@@ -163,7 +163,7 @@ int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd, 
	if ((dw_cmd != PWR_DEEPSLEEP) && (dw_cmd != PWR_EMERGENCYDEEPSLEEP))

		return -EINVAL;



	switch (dev_context->dw_brd_state) {

	switch (dev_context->brd_state) {

	case BRD_RUNNING:

		omap_mbox_save_ctx(dev_context->mbox);

		if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
@@ -223,9 +223,9 @@ int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd, 
	} else {

		/* Update the Bridger Driver state */

		if (dsp_test_sleepstate == PWRDM_POWER_OFF)

			dev_context->dw_brd_state = BRD_HIBERNATION;

			dev_context->brd_state = BRD_HIBERNATION;

		else

			dev_context->dw_brd_state = BRD_RETENTION;

			dev_context->brd_state = BRD_RETENTION;



		/* Disable wdt on hibernation. */

		dsp_wdt_enable(false);
@@ -258,8 +258,8 @@ int wake_dsp(struct bridge_dev_context *dev_context, void *pargs) 
#ifdef CONFIG_PM



	/* Check the board state, if it is not 'SLEEP' then return */

	if (dev_context->dw_brd_state == BRD_RUNNING ||

	    dev_context->dw_brd_state == BRD_STOPPED) {

	if (dev_context->brd_state == BRD_RUNNING ||

	    dev_context->brd_state == BRD_STOPPED) {

		/* The Device is in 'RET' or 'OFF' state and Bridge state is not

		 * 'SLEEP', this means state inconsistency, so return */

		return 0;
@@ -269,7 +269,7 @@ int wake_dsp(struct bridge_dev_context *dev_context, void *pargs) 
	sm_interrupt_dsp(dev_context, MBX_PM_DSPWAKEUP);



	/* Set the device state to RUNNIG */

	dev_context->dw_brd_state = BRD_RUNNING;

	dev_context->brd_state = BRD_RUNNING;

#endif /* CONFIG_PM */

	return status;

}
@@ -351,12 +351,12 @@ int pre_scale_dsp(struct bridge_dev_context *dev_context, void *pargs) 


	dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",

		__func__, voltage_domain, level);

	if ((dev_context->dw_brd_state == BRD_HIBERNATION) ||

	    (dev_context->dw_brd_state == BRD_RETENTION) ||

	    (dev_context->dw_brd_state == BRD_DSP_HIBERNATION)) {

	if ((dev_context->brd_state == BRD_HIBERNATION) ||

	    (dev_context->brd_state == BRD_RETENTION) ||

	    (dev_context->brd_state == BRD_DSP_HIBERNATION)) {

		dev_dbg(bridge, "OPP: %s IVA in sleep. No message to DSP\n");

		return 0;

	} else if ((dev_context->dw_brd_state == BRD_RUNNING)) {

	} else if ((dev_context->brd_state == BRD_RUNNING)) {

		/* Send a prenotificatio to DSP */

		dev_dbg(bridge, "OPP: %s sent notification to DSP\n", __func__);

		sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_PRENOTIFY);
@@ -390,14 +390,14 @@ int post_scale_dsp(struct bridge_dev_context *dev_context, 
	level = *((u32 *) pargs + 1);

	dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",

		__func__, voltage_domain, level);

	if ((dev_context->dw_brd_state == BRD_HIBERNATION) ||

	    (dev_context->dw_brd_state == BRD_RETENTION) ||

	    (dev_context->dw_brd_state == BRD_DSP_HIBERNATION)) {

	if ((dev_context->brd_state == BRD_HIBERNATION) ||

	    (dev_context->brd_state == BRD_RETENTION) ||

	    (dev_context->brd_state == BRD_DSP_HIBERNATION)) {

		/* Update the OPP value in shared memory */

		io_sh_msetting(hio_mgr, SHM_CURROPP, &level);

		dev_dbg(bridge, "OPP: %s IVA in sleep. Wrote to shm\n",

			__func__);

	} else if ((dev_context->dw_brd_state == BRD_RUNNING)) {

	} else if ((dev_context->brd_state == BRD_RUNNING)) {

		/* Update the OPP value in shared memory */

		io_sh_msetting(hio_mgr, SHM_CURROPP, &level);

		/* Send a post notification to DSP */
@@ -486,8 +486,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) 
		writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);

		break;

	case BPWR_MCBSP1:

		iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8);

		mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4);

		iva2_grpsel = readl(resources->core_pm_base + 0xA8);

		mpu_grpsel = readl(resources->core_pm_base + 0xA4);

		if (enable) {

			iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;

			mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
@@ -495,8 +495,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) 
			mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;

			iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;

		}

		writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8);

		writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4);

		writel(iva2_grpsel, resources->core_pm_base + 0xA8);

		writel(mpu_grpsel, resources->core_pm_base + 0xA4);

		break;

	case BPWR_MCBSP2:

		iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);