Commit b537149a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "One new core feature here, a small collection of new drivers and a
  bunch of small improvements in existing drivers:

   - A new CS_WORD flag for transfers where the chip select is toggled
     at every word, with both a generic implementation and the ability
     for controllers to do this automatically (including a DaVinci one).

   - New drivers for Mediatek MT2712, Qualcomm GENI and QSPI, Spreadtrum
     SPI and ST STM32 QSPI plus new IDs for several existing ones"

* tag 'spi-v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (86 commits)
  spi: lpspi: add imx8qxp compatible string
  spi: Allow building SPI_BCM63XX_HSSPI on ARM-based SoCs
  spi: omap2-mcspi: Add slave mode support
  spi: omap2-mcspi: Set FIFO DMA trigger level to word length
  spi: omap2-mcspi: Switch to readl_poll_timeout()
  spi: spi-mem: add stm32 qspi controller
  dt-bindings: spi: add stm32 qspi controller
  spi: sh-msiof: document R8A779{7|8}0 bindings
  spi: pic32-sqi: don't pass GFP_DMA32 to dma_alloc_coherent
  MAINTAINERS: Add entry for Broadcom SPI controller
  spi: sh-msiof: fix deferred probing
  spi: imx: use PIO mode if size is small
  spi: imx: correct wml as the last sg length
  spi: imx: move wml setting to later than setup_transfer
  PCI: Provide pci_match_id() with CONFIG_PCI=n
  spi: Make GPIO CSs honour the SPI_NO_CS flag
  spi/spi-pxa2xx: add PXA2xx SSP SPI Controller
  spi: pxa2xx: Add devicetree support
  spi: pxa2xx: Use an enum for type
  spi: spi-geni-qcom: Add SPI driver support for GENI based QUP
  ...
parents 6214a9fe 7b9734db

Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt

+2 −27
Original line number Diff line number Diff line
@@ -53,20 +53,8 @@ Required properties: 
- clocks:		Serial engine core clock needed by the device.



Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller



Required properties:

- compatible:		Must contain "qcom,geni-spi".

- reg:			Must contain SPI register location and length.

- interrupts:		Must contain SPI controller interrupts.

- clock-names:		Must contain "se".

- clocks:		Serial engine core clock needed by the device.

- spi-max-frequency:	Specifies maximum SPI clock frequency, units - Hz.

- #address-cells:	Must be <1> to define a chip select address on

			the SPI bus.

- #size-cells:		Must be <0>.



SPI slave nodes must be children of the SPI master node and conform to SPI bus

binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.

node binding is described in

Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt.



Example:

	geniqup@8c0000 {
@@ -103,17 +91,4 @@ Example: 
			pinctrl-1 = <&qup_1_uart_3_sleep>;

		};



		spi0: spi@a84000 {

			compatible = "qcom,geni-spi";

			reg = <0xa84000 0x4000>;

			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "se";

			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&qup_1_spi_2_active>;

			pinctrl-1 = <&qup_1_spi_2_sleep>;

			spi-max-frequency = <19200000>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

	}

Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt

0 → 100644
+39 −0
Original line number Diff line number Diff line 
GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)



The QUP v3 core is a GENI based AHB slave that provides a common data path

(an output FIFO and an input FIFO) for serial peripheral interface (SPI)

mini-core.



SPI in master mode supports up to 50MHz, up to four chip selects, programmable

data path from 4 bits to 32 bits and numerous protocol variants.



Required properties:

- compatible:		Must contain "qcom,geni-spi".

- reg:			Must contain SPI register location and length.

- interrupts:		Must contain SPI controller interrupts.

- clock-names:		Must contain "se".

- clocks:		Serial engine core clock needed by the device.

- #address-cells:	Must be <1> to define a chip select address on

			the SPI bus.

- #size-cells:		Must be <0>.



SPI Controller nodes must be child of GENI based Qualcomm Universal

Peripharal. Please refer GENI based QUP wrapper controller node bindings

described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt.



SPI slave nodes must be children of the SPI master node and conform to SPI bus

binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.



Example:

	spi0: spi@a84000 {

		compatible = "qcom,geni-spi";

		reg = <0xa84000 0x4000>;

		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qup_1_spi_2_active>;

		pinctrl-1 = <&qup_1_spi_2_sleep>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
Qualcomm Quad Serial Peripheral Interface (QSPI)



The QSPI controller allows SPI protocol communication in single, dual, or quad

wire transmission modes for read/write access to slaves such as NOR flash.



Required properties:

- compatible:	An SoC specific identifier followed by "qcom,qspi-v1", such as

		"qcom,sdm845-qspi", "qcom,qspi-v1"

- reg:		Should contain the base register location and length.

- interrupts:	Interrupt number used by the controller.

- clocks:	Should contain the core and AHB clock.

- clock-names:	Should be "core" for core clock and "iface" for AHB clock.



SPI slave nodes must be children of the SPI master node and can contain

properties described in Documentation/devicetree/bindings/spi/spi-bus.txt



Example:



	qspi: spi@88df000 {

		compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";

		reg = <0x88df000 0x600>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "iface", "core";

		clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,

			 <&gcc GCC_QSPI_CORE_CLK>;



		flash@0 {

			compatible = "jedec,spi-nor";

			reg = <0>;

			spi-max-frequency = <25000000>;

			spi-tx-bus-width = <2>;

			spi-rx-bus-width = <2>;

		};

	};

Documentation/devicetree/bindings/spi/sh-msiof.txt

+7 −1
Original line number Diff line number Diff line
@@ -2,7 +2,9 @@ Renesas MSIOF spi controller 


Required properties:

- compatible           : "renesas,msiof-r8a7743" (RZ/G1M)

			 "renesas,msiof-r8a7744" (RZ/G1N)

			 "renesas,msiof-r8a7745" (RZ/G1E)

			 "renesas,msiof-r8a774a1" (RZ/G2M)

			 "renesas,msiof-r8a7790" (R-Car H2)

			 "renesas,msiof-r8a7791" (R-Car M2-W)

			 "renesas,msiof-r8a7792" (R-Car V2H)
@@ -11,10 +13,14 @@ Required properties: 
			 "renesas,msiof-r8a7795" (R-Car H3)

			 "renesas,msiof-r8a7796" (R-Car M3-W)

			 "renesas,msiof-r8a77965" (R-Car M3-N)

			 "renesas,msiof-r8a77970" (R-Car V3M)

			 "renesas,msiof-r8a77980" (R-Car V3H)

			 "renesas,msiof-r8a77990" (R-Car E3)

			 "renesas,msiof-r8a77995" (R-Car D3)

			 "renesas,msiof-sh73a0" (SH-Mobile AG5)

			 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)

			 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)

			 "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)

			 "renesas,rcar-gen3-msiof" (generic R-Car Gen3 and RZ/G2 compatible device)

			 "renesas,sh-msiof"      (deprecated)



			 When compatible with the generic version, nodes

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. 


Required properties:

- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or

  "jaguar2"

  "jaguar2", or "amazon,alpine-dw-apb-ssi"

- reg : The register base for the controller. For "mscc,<soc>-spi", a second

  register set is required (named ICPU_CFG:SPI_MST)

- interrupts : One interrupt, used by the controller.