Commit b5b7bef9 authored by Mika Kuoppala's avatar Mika Kuoppala
Browse files

drm/i915/gtt: Use a common type for page directories 



All page directories are identical in function, only the position in the
hierarchy differ. Use same base type for directory functionality.

v2: cleanup, size always 512, init to null

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190614164350.30415-2-mika.kuoppala@linux.intel.com
parent 7d82cc35

drivers/gpu/drm/i915/gem/i915_gem_context.c

+1 −1
Original line number Diff line number Diff line
@@ -1027,7 +1027,7 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data) 


	if (i915_vm_is_4lvl(vm)) {

		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);

		const dma_addr_t pd_daddr = px_dma(&ppgtt->pml4);

		const dma_addr_t pd_daddr = px_dma(ppgtt->pd);



		cs = intel_ring_begin(rq, 6);

		if (IS_ERR(cs))

drivers/gpu/drm/i915/gt/intel_lrc_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 


#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \

	u32 *reg_state__ = (reg_state); \

	const u64 addr__ = px_dma(&ppgtt->pml4); \

	const u64 addr__ = px_dma(ppgtt->pd); \

	(reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \

	(reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \

} while (0)

drivers/gpu/drm/i915/gt/intel_ringbuffer.c

+1 −1
Original line number Diff line number Diff line
@@ -1484,7 +1484,7 @@ static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt) 


	*cs++ = MI_LOAD_REGISTER_IMM(1);

	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

	*cs++ = ppgtt->pd.base.ggtt_offset << 10;

	*cs++ = ppgtt->pd->base.ggtt_offset << 10;



	intel_ring_advance(rq, cs);

drivers/gpu/drm/i915/gvt/scheduler.c

+19 −11
Original line number Diff line number Diff line
@@ -375,11 +375,13 @@ static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, 
		return -EINVAL;



	if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {

		px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];

		px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];

	} else {

		for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {

			px_dma(ppgtt->pdp.page_directory[i]) =

				mm->ppgtt_mm.shadow_pdps[i];

			struct i915_page_directory * const pd =

				i915_pd_entry(ppgtt->pd, i);



			px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];

		}

	}
@@ -1107,11 +1109,14 @@ i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s, 
	int i;



	if (i915_vm_is_4lvl(&ppgtt->vm)) {

		px_dma(&ppgtt->pml4) = s->i915_context_pml4;

		px_dma(ppgtt->pd) = s->i915_context_pml4;

	} else {

		for (i = 0; i < GEN8_3LVL_PDPES; i++)

			px_dma(ppgtt->pdp.page_directory[i]) =

				s->i915_context_pdps[i];

		for (i = 0; i < GEN8_3LVL_PDPES; i++) {

			struct i915_page_directory * const pd =

				i915_pd_entry(ppgtt->pd, i);



			px_dma(pd) = s->i915_context_pdps[i];

		}

	}

}
@@ -1165,11 +1170,14 @@ i915_context_ppgtt_root_save(struct intel_vgpu_submission *s, 
	int i;



	if (i915_vm_is_4lvl(&ppgtt->vm)) {

		s->i915_context_pml4 = px_dma(&ppgtt->pml4);

		s->i915_context_pml4 = px_dma(ppgtt->pd);

	} else {

		for (i = 0; i < GEN8_3LVL_PDPES; i++)

			s->i915_context_pdps[i] =

				px_dma(ppgtt->pdp.page_directory[i]);

		for (i = 0; i < GEN8_3LVL_PDPES; i++) {

			struct i915_page_directory * const pd =

				i915_pd_entry(ppgtt->pd, i);



			s->i915_context_pdps[i] = px_dma(pd);

		}

	}

}

drivers/gpu/drm/i915/i915_gem_gtt.c

+179 −172

File changed.

Preview size limit exceeded, changes collapsed.