Commit b5ef94fb authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/perf' into for-next/core 

* for-next/perf: (25 commits)
  perf/marvell: Fix !CONFIG_OF build for CN10K DDR PMU driver
  drivers/perf: Add Apple icestorm/firestorm CPU PMU driver
  drivers/perf: arm_pmu: Handle 47 bit counters
  arm64: perf: Consistently make all event numbers as 16-bits
  arm64: perf: Expose some Armv9 common events under sysfs
  perf/marvell: cn10k DDR perf event core ownership
  perf/marvell: cn10k DDR perfmon event overflow handling
  perf/marvell: CN10k DDR performance monitor support
  dt-bindings: perf: marvell: cn10k ddr performance monitor
  perf/arm-cmn: Update watchpoint format
  perf/arm-cmn: Hide XP PUB events for CMN-600
  perf: replace bitmap_weight with bitmap_empty where appropriate
  perf: Replace acpi_bus_get_device()
  perf/marvell_cn10k: Fix unused variable warning when W=1 and CONFIG_OF=n
  perf/arm-cmn: Make arm_cmn_debugfs static
  perf: MARVELL_CN10K_TAD_PMU should depend on ARCH_THUNDER
  perf/arm-ccn: Use platform_get_irq() to get the interrupt
  irqchip/apple-aic: Move PMU-specific registers to their own include file
  arm64: dts: apple: Add t8303 PMU nodes
  arm64: dts: apple: Add t8103 PMU interrupt affinities
  ...
parents 292ca2d8 6676a42f

Documentation/devicetree/bindings/arm/pmu.yaml

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ properties: 
    items:

      - enum:

          - apm,potenza-pmu

          - apple,firestorm-pmu

          - apple,icestorm-pmu

          - arm,armv8-pmuv3 # Only for s/w models

          - arm,arm1136-pmu

          - arm,arm1176-pmu

Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml

+31 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ properties: 
          - 1: virtual HV timer

          - 2: physical guest timer

          - 3: virtual guest timer

          - 4: 'efficient' CPU PMU

          - 5: 'performance' CPU PMU



      The 3rd cell contains the interrupt flags. This is normally

      IRQ_TYPE_LEVEL_HIGH (4).
@@ -68,6 +70,35 @@ properties: 
  power-domains:

    maxItems: 1



  affinities:

    type: object

    additionalProperties: false

    description:

      FIQ affinity can be expressed as a single "affinities" node,

      containing a set of sub-nodes, one per FIQ with a non-default

      affinity.

    patternProperties:

      "^.+-affinity$":

        type: object

        additionalProperties: false

        properties:

          apple,fiq-index:

            description:

              The interrupt number specified as a FIQ, and for which

              the affinity is not the default.

            $ref: /schemas/types.yaml#/definitions/uint32

            maximum: 5



          cpus:

            $ref: /schemas/types.yaml#/definitions/phandle-array

            description:

              Should be a list of phandles to CPU nodes (as described in

              Documentation/devicetree/bindings/arm/cpus.yaml).



        required:

          - fiq-index

          - cpus



required:

  - compatible

  - '#interrupt-cells'

Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml

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+37 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell CN10K DDR performance monitor



maintainers:

  - Bharat Bhushan <bbhushan2@marvell.com>



properties:

  compatible:

    items:

      - enum:

          - marvell,cn10k-ddr-pmu



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pmu@87e1c0000000 {

            compatible = "marvell,cn10k-ddr-pmu";

            reg = <0x87e1 0xc0000000 0x0 0x10000>;

        };

    };

arch/arm64/boot/dts/apple/t8103.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -97,6 +97,18 @@ timer { 
			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;

	};



	pmu-e {

		compatible = "apple,icestorm-pmu";

		interrupt-parent = <&aic>;

		interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;

	};



	pmu-p {

		compatible = "apple,firestorm-pmu";

		interrupt-parent = <&aic>;

		interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;

	};



	clkref: clock-ref {

		compatible = "fixed-clock";

		#clock-cells = <0>;
@@ -213,6 +225,18 @@ aic: interrupt-controller@23b100000 { 
			interrupt-controller;

			reg = <0x2 0x3b100000 0x0 0x8000>;

			power-domains = <&ps_aic>;



			affinities {

				e-core-pmu-affinity {

					apple,fiq-index = <AIC_CPU_PMU_E>;

					cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;

				};



				p-core-pmu-affinity {

					apple,fiq-index = <AIC_CPU_PMU_P>;

					cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;

				};

			};

		};



		pmgr: power-management@23b700000 {

arch/arm64/include/asm/apple_m1_pmu.h

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// SPDX-License-Identifier: GPL-2.0



#ifndef __ASM_APPLE_M1_PMU_h

#define __ASM_APPLE_M1_PMU_h



#include <linux/bits.h>

#include <asm/sysreg.h>



/* Counters */

#define SYS_IMP_APL_PMC0_EL1	sys_reg(3, 2, 15, 0, 0)

#define SYS_IMP_APL_PMC1_EL1	sys_reg(3, 2, 15, 1, 0)

#define SYS_IMP_APL_PMC2_EL1	sys_reg(3, 2, 15, 2, 0)

#define SYS_IMP_APL_PMC3_EL1	sys_reg(3, 2, 15, 3, 0)

#define SYS_IMP_APL_PMC4_EL1	sys_reg(3, 2, 15, 4, 0)

#define SYS_IMP_APL_PMC5_EL1	sys_reg(3, 2, 15, 5, 0)

#define SYS_IMP_APL_PMC6_EL1	sys_reg(3, 2, 15, 6, 0)

#define SYS_IMP_APL_PMC7_EL1	sys_reg(3, 2, 15, 7, 0)

#define SYS_IMP_APL_PMC8_EL1	sys_reg(3, 2, 15, 9, 0)

#define SYS_IMP_APL_PMC9_EL1	sys_reg(3, 2, 15, 10, 0)



/* Core PMC control register */

#define SYS_IMP_APL_PMCR0_EL1	sys_reg(3, 1, 15, 0, 0)

#define PMCR0_CNT_ENABLE_0_7	GENMASK(7, 0)

#define PMCR0_IMODE		GENMASK(10, 8)

#define PMCR0_IMODE_OFF		0

#define PMCR0_IMODE_PMI		1

#define PMCR0_IMODE_AIC		2

#define PMCR0_IMODE_HALT	3

#define PMCR0_IMODE_FIQ		4

#define PMCR0_IACT		BIT(11)

#define PMCR0_PMI_ENABLE_0_7	GENMASK(19, 12)

#define PMCR0_STOP_CNT_ON_PMI	BIT(20)

#define PMCR0_CNT_GLOB_L2C_EVT	BIT(21)

#define PMCR0_DEFER_PMI_TO_ERET	BIT(22)

#define PMCR0_ALLOW_CNT_EN_EL0	BIT(30)

#define PMCR0_CNT_ENABLE_8_9	GENMASK(33, 32)

#define PMCR0_PMI_ENABLE_8_9	GENMASK(45, 44)



#define SYS_IMP_APL_PMCR1_EL1	sys_reg(3, 1, 15, 1, 0)

#define PMCR1_COUNT_A64_EL0_0_7	GENMASK(15, 8)

#define PMCR1_COUNT_A64_EL1_0_7	GENMASK(23, 16)

#define PMCR1_COUNT_A64_EL0_8_9	GENMASK(41, 40)

#define PMCR1_COUNT_A64_EL1_8_9	GENMASK(49, 48)



#define SYS_IMP_APL_PMCR2_EL1	sys_reg(3, 1, 15, 2, 0)

#define SYS_IMP_APL_PMCR3_EL1	sys_reg(3, 1, 15, 3, 0)

#define SYS_IMP_APL_PMCR4_EL1	sys_reg(3, 1, 15, 4, 0)



#define SYS_IMP_APL_PMESR0_EL1	sys_reg(3, 1, 15, 5, 0)

#define PMESR0_EVT_CNT_2	GENMASK(7, 0)

#define PMESR0_EVT_CNT_3	GENMASK(15, 8)

#define PMESR0_EVT_CNT_4	GENMASK(23, 16)

#define PMESR0_EVT_CNT_5	GENMASK(31, 24)



#define SYS_IMP_APL_PMESR1_EL1	sys_reg(3, 1, 15, 6, 0)

#define PMESR1_EVT_CNT_6	GENMASK(7, 0)

#define PMESR1_EVT_CNT_7	GENMASK(15, 8)

#define PMESR1_EVT_CNT_8	GENMASK(23, 16)

#define PMESR1_EVT_CNT_9	GENMASK(31, 24)



#define SYS_IMP_APL_PMSR_EL1	sys_reg(3, 1, 15, 13, 0)

#define PMSR_OVERFLOW		GENMASK(9, 0)



#endif /* __ASM_APPLE_M1_PMU_h */