Commit b5f1bf48 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge tag 'powerpc-4.7-5' into next 

Pull in the fixes we sent during 4.7, we have code we want to merge into
next that depends on some of them.
parents 95ec77c0 bfa37087

arch/powerpc/include/asm/book3s/32/pgalloc.h

+0 −1
Original line number Diff line number Diff line
@@ -102,7 +102,6 @@ static inline void pgtable_free_tlb(struct mmu_gather *tlb, 
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,

				  unsigned long address)

{

	tlb_flush_pgtable(tlb, address);

	pgtable_page_dtor(table);

	pgtable_free_tlb(tlb, page_address(table), 0);

}

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
#define HPTE_R_RPN_SHIFT	12

#define HPTE_R_RPN		ASM_CONST(0x0ffffffffffff000)

#define HPTE_R_PP		ASM_CONST(0x0000000000000003)

#define HPTE_R_PPP		ASM_CONST(0x8000000000000003)

#define HPTE_R_N		ASM_CONST(0x0000000000000004)

#define HPTE_R_G		ASM_CONST(0x0000000000000008)

#define HPTE_R_M		ASM_CONST(0x0000000000000010)

arch/powerpc/include/asm/book3s/64/pgalloc.h

+15 −1
Original line number Diff line number Diff line
@@ -110,6 +110,11 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) 
static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,

                                  unsigned long address)

{

	/*

	 * By now all the pud entries should be none entries. So go

	 * ahead and flush the page walk cache

	 */

	flush_tlb_pgtable(tlb, address);

        pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE);

}
@@ -127,6 +132,11 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) 
static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,

                                  unsigned long address)

{

	/*

	 * By now all the pud entries should be none entries. So go

	 * ahead and flush the page walk cache

	 */

	flush_tlb_pgtable(tlb, address);

        return pgtable_free_tlb(tlb, pmd, PMD_CACHE_INDEX);

}
@@ -198,7 +208,11 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) 
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,

				  unsigned long address)

{

	tlb_flush_pgtable(tlb, address);

	/*

	 * By now all the pud entries should be none entries. So go

	 * ahead and flush the page walk cache

	 */

	flush_tlb_pgtable(tlb, address);

	pgtable_free_tlb(tlb, table, 0);

}

arch/powerpc/include/asm/book3s/64/pgtable.h

+1 −0
Original line number Diff line number Diff line
@@ -230,6 +230,7 @@ extern unsigned long __kernel_virt_size; 
#define KERN_VIRT_SIZE  __kernel_virt_size

extern struct page *vmemmap;

extern unsigned long ioremap_bot;

extern unsigned long pci_io_base;

#endif /* __ASSEMBLY__ */



#include <asm/book3s/64/hash.h>

arch/powerpc/include/asm/book3s/64/radix.h

+15 −0
Original line number Diff line number Diff line
@@ -228,5 +228,20 @@ extern void radix__vmemmap_remove_mapping(unsigned long start, 


extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,

				 pgprot_t flags, unsigned int psz);



static inline unsigned long radix__get_tree_size(void)

{

	unsigned long rts_field;

	/*

	 * we support 52 bits, hence 52-31 = 21, 0b10101

	 * RTS encoding details

	 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long

	 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long

	 */

	rts_field = (0x5UL << 5); /* 6 - 8 bits */

	rts_field |= (0x2UL << 61);



	return rts_field;

}

#endif /* __ASSEMBLY__ */

#endif