Commit b6f4e451 authored by Denys Vlasenko's avatar Denys Vlasenko Committed by Michal Marek
Browse files

Rename special text sections in arch/frv from .text.XXX to .text..XXX.

parent a7df554e
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+1 −1
Original line number Original line Diff line number Diff line
@@ -63,7 +63,7 @@ __break_trace_through_exceptions:
# entry point for Break Exceptions/Interrupts
# entry point for Break Exceptions/Interrupts
#
#
###############################################################################
###############################################################################
	.section	.text.break
	.section	.text..break
	.balign		4
	.balign		4
	.globl		__entry_break
	.globl		__entry_break
__entry_break:
__entry_break:
+1 −1
Original line number Original line Diff line number Diff line
@@ -38,7 +38,7 @@


#define nr_syscalls ((syscall_table_size)/4)
#define nr_syscalls ((syscall_table_size)/4)


	.section	.text.entry
	.section	.text..entry
	.balign		4
	.balign		4


.macro LEDS val
.macro LEDS val
+1 −1
Original line number Original line Diff line number Diff line
@@ -542,7 +542,7 @@ __head_end:
	.size		_boot, .-_boot
	.size		_boot, .-_boot


	# provide a point for GDB to place a break
	# provide a point for GDB to place a break
	.section	.text.start,"ax"
	.section	.text..start,"ax"
	.globl		_start
	.globl		_start
	.balign		4
	.balign		4
_start:
_start:
+4 −4
Original line number Original line Diff line number Diff line
@@ -57,10 +57,10 @@ SECTIONS
  _text = .;
  _text = .;
  _stext = .;
  _stext = .;
  .text : {
  .text : {
	*(.text.start)
	*(.text..start)
	*(.text.entry)
	*(.text..entry)
	*(.text.break)
	*(.text..break)
	*(.text.tlbmiss)
	*(.text..tlbmiss)
	TEXT_TEXT
	TEXT_TEXT
	SCHED_TEXT
	SCHED_TEXT
	LOCK_TEXT
	LOCK_TEXT
+1 −1
Original line number Original line Diff line number Diff line
@@ -15,7 +15,7 @@
#include <asm/pgtable.h>
#include <asm/pgtable.h>
#include <asm/spr-regs.h>
#include <asm/spr-regs.h>


	.section	.text.tlbmiss
	.section	.text..tlbmiss
	.balign		4
	.balign		4


	.globl		__entry_insn_mmu_miss
	.globl		__entry_insn_mmu_miss