Commit b82b3993 authored by Dafna Hirschfeld's avatar Dafna Hirschfeld Committed by Mauro Carvalho Chehab
Browse files

media: staging: rkisp1: cap: change the logic for writing to uv swap register 



The register RKISP1_CIF_MI_XTD_FORMAT_CTRL is currently written
with "on" only if the u,v streams need to be swapped. This patch
also write to it with "off" if they don't need to be swapped.

Signed-off-by: default avatarDafna Hirschfeld <dafna.hirschfeld@collabora.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent a557c3fa

drivers/staging/media/rkisp1/rkisp1-capture.c

+11 −10
Original line number Diff line number Diff line
@@ -383,12 +383,12 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap) 
		     cap->config->mi.cr_size_init);



	rkisp1_irq_frame_end_enable(cap);

	if (cap->pix.cfg->uv_swap) {

	reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);



	if (cap->pix.cfg->uv_swap)

		reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;

	else

		reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;

	rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);

	}



	rkisp1_mi_config_ctrl(cap);
@@ -406,7 +406,7 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap) 
{

	const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;

	struct rkisp1_device *rkisp1 = cap->rkisp1;

	u32 mi_ctrl;

	u32 mi_ctrl, reg;



	rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),

		     cap->config->mi.y_size_init);
@@ -420,12 +420,13 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap) 
	rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH);



	rkisp1_irq_frame_end_enable(cap);

	if (cap->pix.cfg->uv_swap) {

		u32 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);



	reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);

	if (cap->pix.cfg->uv_swap)

		reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;

	else

		reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;

	rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);

	}



	rkisp1_mi_config_ctrl(cap);