Commit b881955b authored by Divy Le Ray's avatar Divy Le Ray Committed by David S. Miller
Browse files

cxgb3 - parity initialization for T3C adapters. 



Add parity initialization for T3C adapters.

Signed-off-by: default avatarDivy Le Ray <divy@chelsio.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 06daa168

drivers/net/cxgb3/adapter.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ enum { /* adapter flags */ 
	USING_MSI = (1 << 1),

	USING_MSIX = (1 << 2),

	QUEUES_BOUND = (1 << 3),

	TP_PARITY_INIT = (1 << 4),

};



struct fl_pg_chunk {

drivers/net/cxgb3/cxgb3_main.c

+82 −0
Original line number Diff line number Diff line
@@ -306,6 +306,77 @@ static int request_msix_data_irqs(struct adapter *adap) 
	return 0;

}



static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,

			      unsigned long n)

{

	int attempts = 5;



	while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {

		if (!--attempts)

			return -ETIMEDOUT;

		msleep(10);

	}

	return 0;

}



static int init_tp_parity(struct adapter *adap)

{

	int i;

	struct sk_buff *skb;

	struct cpl_set_tcb_field *greq;

	unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;



	t3_tp_set_offload_mode(adap, 1);



	for (i = 0; i < 16; i++) {

		struct cpl_smt_write_req *req;



		skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);

		req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));

		memset(req, 0, sizeof(*req));

		req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));

		OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));

		req->iff = i;

		t3_mgmt_tx(adap, skb);

	}



	for (i = 0; i < 2048; i++) {

		struct cpl_l2t_write_req *req;



		skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);

		req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));

		memset(req, 0, sizeof(*req));

		req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));

		OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));

		req->params = htonl(V_L2T_W_IDX(i));

		t3_mgmt_tx(adap, skb);

	}



	for (i = 0; i < 2048; i++) {

		struct cpl_rte_write_req *req;



		skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);

		req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));

		memset(req, 0, sizeof(*req));

		req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));

		OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));

		req->l2t_idx = htonl(V_L2T_W_IDX(i));

		t3_mgmt_tx(adap, skb);

	}



	skb = alloc_skb(sizeof(*greq), GFP_KERNEL | __GFP_NOFAIL);

	greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));

	memset(greq, 0, sizeof(*greq));

	greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));

	OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));

	greq->mask = cpu_to_be64(1);

	t3_mgmt_tx(adap, skb);



	i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);

	t3_tp_set_offload_mode(adap, 0);

	return i;

}



/**

 *	setup_rss - configure RSS

 *	@adap: the adapter
@@ -817,6 +888,7 @@ static int cxgb_up(struct adapter *adap) 
		if (err)

			goto out;



		t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);

		t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));



		err = setup_sge_qsets(adap);
@@ -856,6 +928,16 @@ static int cxgb_up(struct adapter *adap) 
	t3_sge_start(adap);

	t3_intr_enable(adap);



	if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&

	    is_offload(adap) && init_tp_parity(adap) == 0)

		adap->flags |= TP_PARITY_INIT;



	if (adap->flags & TP_PARITY_INIT) {

		t3_write_reg(adap, A_TP_INT_CAUSE,

			     F_CMCACHEPERR | F_ARPLUTPERR);

		t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);

	}



	if ((adap->flags & (USING_MSIX | QUEUES_BOUND)) == USING_MSIX)

		bind_qsets(adap);

	adap->flags |= QUEUES_BOUND;

drivers/net/cxgb3/cxgb3_offload.c

+13 −2
Original line number Diff line number Diff line
@@ -403,8 +403,6 @@ static int cxgb_offload_ctl(struct t3cdev *tdev, unsigned int req, void *data) 
static int rx_offload_blackhole(struct t3cdev *dev, struct sk_buff **skbs,

				int n)

{

	CH_ERR(tdev2adap(dev), "%d unexpected offload packets, first data %u\n",

	       n, ntohl(*(__be32 *)skbs[0]->data));

	while (n--)

		dev_kfree_skb_any(skbs[n]);

	return 0;
@@ -634,6 +632,18 @@ static int do_l2t_write_rpl(struct t3cdev *dev, struct sk_buff *skb) 
	return CPL_RET_BUF_DONE;

}



static int do_rte_write_rpl(struct t3cdev *dev, struct sk_buff *skb)

{

	struct cpl_rte_write_rpl *rpl = cplhdr(skb);



	if (rpl->status != CPL_ERR_NONE)

		printk(KERN_ERR

		       "Unexpected RTE_WRITE_RPL status %u for entry %u\n",

		       rpl->status, GET_TID(rpl));



	return CPL_RET_BUF_DONE;

}



static int do_act_open_rpl(struct t3cdev *dev, struct sk_buff *skb)

{

	struct cpl_act_open_rpl *rpl = cplhdr(skb);
@@ -1257,6 +1267,7 @@ void __init cxgb3_offload_init(void) 


	t3_register_cpl_handler(CPL_SMT_WRITE_RPL, do_smt_write_rpl);

	t3_register_cpl_handler(CPL_L2T_WRITE_RPL, do_l2t_write_rpl);

	t3_register_cpl_handler(CPL_RTE_WRITE_RPL, do_rte_write_rpl);

	t3_register_cpl_handler(CPL_PASS_OPEN_RPL, do_stid_rpl);

	t3_register_cpl_handler(CPL_CLOSE_LISTSRV_RPL, do_stid_rpl);

	t3_register_cpl_handler(CPL_PASS_ACCEPT_REQ, do_cr);

drivers/net/cxgb3/regs.h

+245 −3
Original line number Diff line number Diff line 
#define A_SG_CONTROL 0x0



#define S_CONGMODE    29

#define V_CONGMODE(x) ((x) << S_CONGMODE)

#define F_CONGMODE    V_CONGMODE(1U)



#define S_TNLFLMODE    28

#define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)

#define F_TNLFLMODE    V_TNLFLMODE(1U)



#define S_FATLPERREN    27

#define V_FATLPERREN(x) ((x) << S_FATLPERREN)

#define F_FATLPERREN    V_FATLPERREN(1U)



#define S_DROPPKT    20

#define V_DROPPKT(x) ((x) << S_DROPPKT)

#define F_DROPPKT    V_DROPPKT(1U)
@@ -172,6 +184,64 @@ 


#define A_SG_INT_CAUSE 0x5c



#define S_HIRCQPARITYERROR    31

#define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)

#define F_HIRCQPARITYERROR    V_HIRCQPARITYERROR(1U)



#define S_LORCQPARITYERROR    30

#define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)

#define F_LORCQPARITYERROR    V_LORCQPARITYERROR(1U)



#define S_HIDRBPARITYERROR    29

#define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)

#define F_HIDRBPARITYERROR    V_HIDRBPARITYERROR(1U)



#define S_LODRBPARITYERROR    28

#define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)

#define F_LODRBPARITYERROR    V_LODRBPARITYERROR(1U)



#define S_FLPARITYERROR    22

#define M_FLPARITYERROR    0x3f

#define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)

#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)



#define S_ITPARITYERROR    20

#define M_ITPARITYERROR    0x3

#define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)

#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)



#define S_IRPARITYERROR    19

#define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)

#define F_IRPARITYERROR    V_IRPARITYERROR(1U)



#define S_RCPARITYERROR    18

#define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)

#define F_RCPARITYERROR    V_RCPARITYERROR(1U)



#define S_OCPARITYERROR    17

#define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)

#define F_OCPARITYERROR    V_OCPARITYERROR(1U)



#define S_CPPARITYERROR    16

#define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)

#define F_CPPARITYERROR    V_CPPARITYERROR(1U)



#define S_R_REQ_FRAMINGERROR    15

#define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)

#define F_R_REQ_FRAMINGERROR    V_R_REQ_FRAMINGERROR(1U)



#define S_UC_REQ_FRAMINGERROR    14

#define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)

#define F_UC_REQ_FRAMINGERROR    V_UC_REQ_FRAMINGERROR(1U)



#define S_HICTLDRBDROPERR    13

#define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)

#define F_HICTLDRBDROPERR    V_HICTLDRBDROPERR(1U)



#define S_LOCTLDRBDROPERR    12

#define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)

#define F_LOCTLDRBDROPERR    V_LOCTLDRBDROPERR(1U)



#define S_HIPIODRBDROPERR    11

#define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)

#define F_HIPIODRBDROPERR    V_HIPIODRBDROPERR(1U)
@@ -286,6 +356,10 @@ 


#define A_PCIX_CFG 0x88



#define S_DMASTOPEN    19

#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)

#define F_DMASTOPEN    V_DMASTOPEN(1U)



#define S_CLIDECEN    18

#define V_CLIDECEN(x) ((x) << S_CLIDECEN)

#define F_CLIDECEN    V_CLIDECEN(1U)
@@ -313,6 +387,22 @@ 


#define V_BISTERR(x) ((x) << S_BISTERR)



#define S_TXPARERR    18

#define V_TXPARERR(x) ((x) << S_TXPARERR)

#define F_TXPARERR    V_TXPARERR(1U)



#define S_RXPARERR    17

#define V_RXPARERR(x) ((x) << S_RXPARERR)

#define F_RXPARERR    V_RXPARERR(1U)



#define S_RETRYLUTPARERR    16

#define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)

#define F_RETRYLUTPARERR    V_RETRYLUTPARERR(1U)



#define S_RETRYBUFPARERR    15

#define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)

#define F_RETRYBUFPARERR    V_RETRYBUFPARERR(1U)



#define S_PCIE_MSIXPARERR    12

#define M_PCIE_MSIXPARERR    0x7
@@ -348,6 +438,10 @@ 


#define A_PCIE_INT_CAUSE 0x84



#define S_PCIE_DMASTOPEN    24

#define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)

#define F_PCIE_DMASTOPEN    V_PCIE_DMASTOPEN(1U)



#define A_PCIE_CFG 0x88



#define S_PCIE_CLIDECEN    16
@@ -741,6 +835,54 @@ 


#define A_CIM_HOST_INT_ENABLE 0x298



#define S_DTAGPARERR    28

#define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)

#define F_DTAGPARERR    V_DTAGPARERR(1U)



#define S_ITAGPARERR    27

#define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)

#define F_ITAGPARERR    V_ITAGPARERR(1U)



#define S_IBQTPPARERR    26

#define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)

#define F_IBQTPPARERR    V_IBQTPPARERR(1U)



#define S_IBQULPPARERR    25

#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)

#define F_IBQULPPARERR    V_IBQULPPARERR(1U)



#define S_IBQSGEHIPARERR    24

#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)

#define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)



#define S_IBQSGELOPARERR    23

#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)

#define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)



#define S_OBQULPLOPARERR    22

#define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)

#define F_OBQULPLOPARERR    V_OBQULPLOPARERR(1U)



#define S_OBQULPHIPARERR    21

#define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)

#define F_OBQULPHIPARERR    V_OBQULPHIPARERR(1U)



#define S_OBQSGEPARERR    20

#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)

#define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)



#define S_DCACHEPARERR    19

#define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)

#define F_DCACHEPARERR    V_DCACHEPARERR(1U)



#define S_ICACHEPARERR    18

#define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)

#define F_ICACHEPARERR    V_ICACHEPARERR(1U)



#define S_DRAMPARERR    17

#define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)

#define F_DRAMPARERR    V_DRAMPARERR(1U)



#define A_CIM_HOST_INT_CAUSE 0x29c



#define S_BLKWRPLINT    12
@@ -799,8 +941,42 @@ 


#define A_CIM_HOST_ACC_DATA 0x2b4



#define A_CIM_IBQ_DBG_CFG 0x2c0



#define S_IBQDBGADDR    16

#define M_IBQDBGADDR    0x1ff

#define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)

#define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)



#define S_IBQDBGQID    3

#define M_IBQDBGQID    0x3

#define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)

#define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)



#define S_IBQDBGWR    2

#define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)

#define F_IBQDBGWR    V_IBQDBGWR(1U)



#define S_IBQDBGBUSY    1

#define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)

#define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)



#define S_IBQDBGEN    0

#define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)

#define F_IBQDBGEN    V_IBQDBGEN(1U)



#define A_CIM_IBQ_DBG_DATA 0x2c8



#define A_TP_IN_CONFIG 0x300



#define S_RXFBARBPRIO    25

#define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)

#define F_RXFBARBPRIO    V_RXFBARBPRIO(1U)



#define S_TXFBARBPRIO    24

#define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)

#define F_TXFBARBPRIO    V_TXFBARBPRIO(1U)



#define S_NICMODE    14

#define V_NICMODE(x) ((x) << S_NICMODE)

#define F_NICMODE    V_NICMODE(1U)
@@ -973,6 +1149,22 @@ 


#define A_TP_PC_CONFIG2 0x34c



#define S_DISBLEDAPARBIT0    15

#define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)

#define F_DISBLEDAPARBIT0    V_DISBLEDAPARBIT0(1U)



#define S_ENABLEARPMISS    13

#define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)

#define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)



#define S_ENABLENONOFDTNLSYN    12

#define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)

#define F_ENABLENONOFDTNLSYN    V_ENABLENONOFDTNLSYN(1U)



#define S_ENABLEIPV6RSS    11

#define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)

#define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)



#define S_CHDRAFULL    4

#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)

#define F_CHDRAFULL    V_CHDRAFULL(1U)
@@ -1024,6 +1216,12 @@ 


#define A_TP_PARA_REG4 0x370



#define A_TP_PARA_REG5 0x374



#define S_RXDDPOFFINIT    3

#define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)

#define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)



#define A_TP_PARA_REG6 0x378



#define S_T3A_ENABLEESND    13
@@ -1144,6 +1342,10 @@ 
#define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)

#define F_TNLLKPEN    V_TNLLKPEN(1U)



#define S_RRCPLMAPEN    7

#define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)

#define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)



#define S_RRCPLCPUSIZE    4

#define M_RRCPLCPUSIZE    0x7

#define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
@@ -1216,6 +1418,14 @@ 
#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)

#define F_FLMRXFLSTEMPTY    V_FLMRXFLSTEMPTY(1U)



#define S_ARPLUTPERR    26

#define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)

#define F_ARPLUTPERR    V_ARPLUTPERR(1U)



#define S_CMCACHEPERR    24

#define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)

#define F_CMCACHEPERR    V_CMCACHEPERR(1U)



#define A_TP_INT_CAUSE 0x474



#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
@@ -1259,9 +1469,37 @@ 


#define A_ULPRX_INT_ENABLE 0x504



#define S_PARERR    0

#define V_PARERR(x) ((x) << S_PARERR)

#define F_PARERR    V_PARERR(1U)

#define S_DATASELFRAMEERR0    7

#define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)

#define F_DATASELFRAMEERR0    V_DATASELFRAMEERR0(1U)



#define S_DATASELFRAMEERR1    6

#define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)

#define F_DATASELFRAMEERR1    V_DATASELFRAMEERR1(1U)



#define S_PCMDMUXPERR    5

#define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)

#define F_PCMDMUXPERR    V_PCMDMUXPERR(1U)



#define S_ARBFPERR    4

#define V_ARBFPERR(x) ((x) << S_ARBFPERR)

#define F_ARBFPERR    V_ARBFPERR(1U)



#define S_ARBPF0PERR    3

#define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)

#define F_ARBPF0PERR    V_ARBPF0PERR(1U)



#define S_ARBPF1PERR    2

#define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)

#define F_ARBPF1PERR    V_ARBPF1PERR(1U)



#define S_PARERRPCMD    1

#define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)

#define F_PARERRPCMD    V_PARERRPCMD(1U)



#define S_PARERRDATA    0

#define V_PARERRDATA(x) ((x) << S_PARERRDATA)

#define F_PARERRDATA    V_PARERRDATA(1U)



#define A_ULPRX_INT_CAUSE 0x508
@@ -1559,6 +1797,10 @@ 


#define A_CPL_INTR_ENABLE 0x650



#define S_CIM_OP_MAP_PERR    5

#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)

#define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)



#define S_CIM_OVFL_ERROR    4

#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)

#define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)

drivers/net/cxgb3/sge.c

+20 −4
Original line number Diff line number Diff line
@@ -2443,6 +2443,15 @@ irq_handler_t t3_intr_handler(struct adapter *adap, int polling) 
	return t3_intr;

}



#define SGE_PARERR (F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \

		    F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \

		    V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \

		    F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \

		    F_HIRCQPARITYERROR)

#define SGE_FRAMINGERR (F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR)

#define SGE_FATALERR (SGE_PARERR | SGE_FRAMINGERR | F_RSPQCREDITOVERFOW | \

		      F_RSPQDISABLED)



/**

 *	t3_sge_err_intr_handler - SGE async event interrupt handler

 *	@adapter: the adapter
@@ -2453,6 +2462,13 @@ void t3_sge_err_intr_handler(struct adapter *adapter) 
{

	unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE);



	if (status & SGE_PARERR)

		CH_ALERT(adapter, "SGE parity error (0x%x)\n",

			 status & SGE_PARERR);

	if (status & SGE_FRAMINGERR)

		CH_ALERT(adapter, "SGE framing error (0x%x)\n",

			 status & SGE_FRAMINGERR);



	if (status & F_RSPQCREDITOVERFOW)

		CH_ALERT(adapter, "SGE response queue credit overflow\n");
@@ -2469,7 +2485,7 @@ void t3_sge_err_intr_handler(struct adapter *adapter) 
			 status & F_HIPIODRBDROPERR ? "high" : "lo");



	t3_write_reg(adapter, A_SG_INT_CAUSE, status);

	if (status & (F_RSPQCREDITOVERFOW | F_RSPQDISABLED))

	if (status &  SGE_FATALERR)

		t3_fatal_err(adapter);

}
@@ -2781,7 +2797,7 @@ void t3_sge_init(struct adapter *adap, struct sge_params *p) 
	unsigned int ctrl, ups = ffs(pci_resource_len(adap->pdev, 2) >> 12);



	ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |

	    F_CQCRDTCTRL |

	    F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN |

	    V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS |

	    V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING;

#if SGE_NUM_GENBITS == 1
@@ -2790,7 +2806,6 @@ void t3_sge_init(struct adapter *adap, struct sge_params *p) 
	if (adap->params.rev > 0) {

		if (!(adap->flags & (USING_MSIX | USING_MSI)))

			ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;

		ctrl |= F_CQCRDTCTRL | F_AVOIDCQOVFL;

	}

	t3_write_reg(adap, A_SG_CONTROL, ctrl);

	t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
@@ -2798,7 +2813,8 @@ void t3_sge_init(struct adapter *adap, struct sge_params *p) 
	t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);

	t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |

		     V_TIMEOUT(200 * core_ticks_per_usec(adap)));

	t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH, 1000);

	t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH,

		     adap->params.rev < T3_REV_C ? 1000 : 500);

	t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);

	t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);

	t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);