Commit b900352f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.19-2022-04-29' of... 

Merge tag 'amd-drm-next-5.19-2022-04-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.19-2022-04-29:

amdgpu
- RAS updates
- SI dpm deadlock fix
- Misc code cleanups
- HDCP fixes
- PSR fixes
- DSC fixes
- SDMA doorbell cleanups
- S0ix fix
- DC FP fix
- Zen dom0 regression fix for APUs
- IP discovery updates
- Initial SoC21 support
- Support for new vbios tables
- Runtime PM fixes
- Add PSP TA debugfs interface

amdkfd:
- Misc code cleanups
- Ignore bogus MEC signals more efficiently
- SVM fixes
- Use bitmap helpers

radeon:
- Misc code cleanups
- Spelling/grammer fixes

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220429144853.5742-1-alexander.deucher@amd.com
parents 8d62a974 3da2c382

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce 
amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o



# add DF block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −1
Original line number Diff line number Diff line
@@ -666,10 +666,13 @@ enum amd_hw_ip_block_type { 
	MAX_HWIP

};



#define HWIP_MAX_INSTANCE	10

#define HWIP_MAX_INSTANCE	11



#define HW_ID_MAX		300

#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))

#define IP_VERSION_MAJ(ver) ((ver) >> 16)

#define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)

#define IP_VERSION_REV(ver) ((ver) & 0xFF)



struct amd_powerplay {

	void *pp_handle;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+246 −125
Original line number Diff line number Diff line
@@ -162,12 +162,14 @@ union vram_info { 
	struct atom_vram_info_header_v2_4 v24;

	struct atom_vram_info_header_v2_5 v25;

	struct atom_vram_info_header_v2_6 v26;

	struct atom_vram_info_header_v3_0 v30;

};



union vram_module {

	struct atom_vram_module_v9 v9;

	struct atom_vram_module_v10 v10;

	struct atom_vram_module_v11 v11;

	struct atom_vram_module_v3_0 v30;

};



static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
@@ -294,7 +296,28 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
			vram_info = (union vram_info *)

				(mode_info->atom_context->bios + data_offset);

			module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;

			if (frev == 3) {

				switch (crev) {

				/* v30 */

				case 0:

					vram_module = (union vram_module *)vram_info->v30.vram_module;

					mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;

					if (vram_vendor)

						*vram_vendor = mem_vendor;

					mem_type = vram_info->v30.memory_type;

					if (vram_type)

						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);

					mem_channel_number = vram_info->v30.channel_num;

					mem_channel_width = vram_info->v30.channel_width;

					if (vram_width)

						*vram_width = mem_channel_number * mem_channel_width;

					break;

				default:

					return -EINVAL;

				}

			} else if (frev == 2) {

				switch (crev) {

				/* v23 */

				case 3:

					if (module_id > vram_info->v23.vram_module_num)

						module_id = 0;
@@ -315,6 +338,7 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
					if (vram_vendor)

						*vram_vendor = mem_vendor;

					break;

				/* v24 */

				case 4:

					if (module_id > vram_info->v24.vram_module_num)

						module_id = 0;
@@ -335,6 +359,7 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
					if (vram_vendor)

						*vram_vendor = mem_vendor;

					break;

				/* v25 */

				case 5:

					if (module_id > vram_info->v25.vram_module_num)

						module_id = 0;
@@ -355,6 +380,7 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
					if (vram_vendor)

						*vram_vendor = mem_vendor;

					break;

				/* v26 */

				case 6:

					if (module_id > vram_info->v26.vram_module_num)

						module_id = 0;
@@ -378,6 +404,10 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
				default:

					return -EINVAL;

				}

			} else {

				/* invalid frev */

				return -EINVAL;

			}

		}



	}
@@ -528,6 +558,13 @@ union smu_info { 
	struct atom_smu_info_v3_1 v31;

};



union gfx_info {

	struct atom_gfx_info_v2_2 v22;

	struct atom_gfx_info_v2_4 v24;

	struct atom_gfx_info_v2_7 v27;

	struct atom_gfx_info_v3_0 v30;

};



int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;
@@ -609,22 +646,26 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) 
						   gfx_info);

		if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,

					  &frev, &crev, &data_offset)) {

			struct atom_gfx_info_v2_2 *gfx_info = (struct atom_gfx_info_v2_2*)

			union gfx_info *gfx_info = (union gfx_info *)

				(mode_info->atom_context->bios + data_offset);

			if ((frev == 2) && (crev >= 2))

				spll->reference_freq = le32_to_cpu(gfx_info->rlc_gpu_timer_refclk);

			if ((frev == 3) ||

			    (frev == 2 && crev == 6)) {

				spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);

				ret = 0;

			} else if ((frev == 2) &&

				   (crev >= 2) &&

				   (crev != 6)) {

				spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);

				ret = 0;

			} else {

				BUG();

			}

		}

	}



	return ret;

}



union gfx_info {

	struct atom_gfx_info_v2_4 v24;

	struct atom_gfx_info_v2_7 v27;

};



int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;
@@ -638,6 +679,7 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) 
				   &frev, &crev, &data_offset)) {

		union gfx_info *gfx_info = (union gfx_info *)

			(mode_info->atom_context->bios + data_offset);

		if (frev == 2) {

			switch (crev) {

			case 4:

				adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
@@ -676,6 +718,21 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) 
			default:

				return -EINVAL;

			}

		} else if (frev == 3) {

			switch (crev) {

			case 0:

				adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;

				adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;

				adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;

				adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;

				adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;

				return 0;

			default:

				return -EINVAL;

			}

		} else {

			return -EINVAL;

		}



	}

	return -EINVAL;
@@ -731,3 +788,67 @@ int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev) 


	return fw_reserved_fb_size;

}



/*

 * Helper function to execute asic_init table

 *

 * @adev: amdgpu_device pointer

 * @fb_reset: flag to indicate whether fb is reset or not

 *

 * Return 0 if succeed, otherwise failed

 */

int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	struct atom_context *ctx;

	uint8_t frev, crev;

	uint16_t data_offset;

	uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;

	struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;

	int index;



	if (!mode_info)

		return -EINVAL;



	ctx = mode_info->atom_context;

	if (!ctx)

		return -EINVAL;



	/* query bootup sclk/mclk from firmware_info table */

	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

					    firmwareinfo);

	if (amdgpu_atom_parse_data_header(ctx, index, NULL,

				&frev, &crev, &data_offset)) {

		union firmware_info *firmware_info =

			(union firmware_info *)(ctx->bios +

						data_offset);



		bootup_sclk_in10khz =

			le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);

		bootup_mclk_in10khz =

			le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);

	} else {

		return -EINVAL;

	}



	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,

                                            asic_init);

	if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {

		if (frev == 2 && crev >= 1) {

			memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));

			asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;

			asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;

			asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;

			if (!fb_reset)

				asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;

			else

				asic_init_ps_v2_1.param.memparam.memflag = 0;

		} else {

			return -EINVAL;

		}

	} else {

		return -EINVAL;

	}



	return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

+1 −0
Original line number Diff line number Diff line
@@ -40,5 +40,6 @@ bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t* i2c_a 
bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev);

bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev);

int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev);

int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset);



#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

+11 −2
Original line number Diff line number Diff line
@@ -471,6 +471,7 @@ bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 
{

	u32 *dw_ptr;

	u32 i, length_dw;

	u32 rom_offset;

	u32 rom_index_offset;

	u32 rom_data_offset;
@@ -494,8 +495,16 @@ bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 
	rom_data_offset =

		adev->smuio.funcs->get_rom_data_offset(adev);



	/* set rom index to 0 */

	WREG32(rom_index_offset, 0);

	if (adev->nbio.funcs &&

	    adev->nbio.funcs->get_rom_offset) {

		rom_offset = adev->nbio.funcs->get_rom_offset(adev);

		rom_offset = rom_offset << 17;

	} else {

		rom_offset = 0;

	}



	/* set rom index to rom_offset */

	WREG32(rom_index_offset, rom_offset);

	/* read out the rom data */

	for (i = 0; i < length_dw; i++)

		dw_ptr[i] = RREG32(rom_data_offset);