Commit b90cb538 authored by Omkar Kulkarni's avatar Omkar Kulkarni Committed by David S. Miller
Browse files

qed: Update FW init functions to support FW 8.59.1.0 



The qed_init_fw_func.c and qed_init_ops.c updated to support FW
version 8.59.1.0.
  - Support 16-bit VPORT WFQ (weighted fair queueing) weights.
  - Support WFQ (weighted fair queueing) weight per VPORT + TC.
  - Support allocation of Tx PQs(physical queues) per PF,VF.
  - Modify Global RL (rate limiter) upper bound configuration.
  - Update FW operation functions.
  - Update iro_arr[] array.

This patch also fixes the existing checkpatch warnings and few important
checks.

Signed-off-by: default avatarAriel Elior <aelior@marvell.com>
Signed-off-by: default avatarShai Malin <smalin@marvell.com>
Signed-off-by: default avatarOmkar Kulkarni <okulkarni@marvell.com>
Signed-off-by: default avatarPrabhakar Kushwaha <pkushwaha@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3091be06

drivers/net/ethernet/qlogic/qed/qed.h

+11 −13
Original line number Diff line number Diff line
@@ -91,14 +91,14 @@ static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 
}



#define ALIGNED_TYPE_SIZE(type_name, p_hwfn)				     \

	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \

	((sizeof(type_name) + (u32)(1 << ((p_hwfn)->cdev->cache_shift)) - 1) & \

	 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))



#define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)

#define for_each_hwfn(cdev, i)  for (i = 0; i < (cdev)->num_hwfns; i++)



#define D_TRINE(val, cond1, cond2, true1, true2, def) \

	(val == (cond1) ? true1 :		      \

	 (val == (cond2) ? true2 : def))

	((val) == (cond1) ? true1 :		      \

	 ((val) == (cond2) ? true2 : def))



/* forward */

struct qed_ptt_pool;
@@ -512,7 +512,7 @@ enum qed_hsi_def_type { 


struct qed_simd_fp_handler {

	void	*token;

	void	(*func)(void *);

	void	(*func)(void *cookie);

};



enum qed_slowpath_wq_flag {
@@ -875,7 +875,6 @@ u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type); 
#define NUM_OF_BTB_BLOCKS(dev) \

	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)





/**

 * qed_concrete_to_sw_fid(): Get the sw function id from

 *                           the concrete value.
@@ -903,7 +902,6 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 
}



#define PKT_LB_TC	9

#define MAX_NUM_VOQS	20



int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);

void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
@@ -915,7 +913,7 @@ int qed_device_num_engines(struct qed_dev *cdev); 
void qed_set_fw_mac_addr(__le16 *fw_msb,

			 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);



#define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])

#define QED_LEADING_HWFN(dev)   (&(dev)->hwfns[0])

#define QED_IS_CMT(dev)		((dev)->num_hwfns > 1)

/* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */

#define QED_FIR_AFFIN_HWFN(dev)		(&(dev)->hwfns[dev->fir_affin])
@@ -936,7 +934,7 @@ void qed_set_fw_mac_addr(__le16 *fw_msb, 
#define PQ_FLAGS_LLT    (BIT(7))

#define PQ_FLAGS_MTC    (BIT(8))



/* physical queue index for cm context intialization */

/* physical queue index for cm context initialization */

u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);

u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);

u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
@@ -951,9 +949,9 @@ bool qed_edpm_enabled(struct qed_hwfn *p_hwfn); 
/* Other Linux specific common definitions */

#define DP_NAME(cdev) ((cdev)->name)



#define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\

						(cdev->regview) + \

							 (offset))

#define REG_ADDR(cdev, offset)          ((void __iomem *)((u8 __iomem *)\

						((cdev)->regview) + \

							 (offset)))



#define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))

#define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
@@ -961,7 +959,7 @@ bool qed_edpm_enabled(struct qed_hwfn *p_hwfn); 


#define DOORBELL(cdev, db_addr, val)			 \

	writel((u32)val, (void __iomem *)((u8 __iomem *)\

					  (cdev->doorbells) + (db_addr)))

					  ((cdev)->doorbells) + (db_addr)))



#define MFW_PORT(_p_hwfn)       ((_p_hwfn)->abs_pf_id %			  \

				  qed_device_num_ports((_p_hwfn)->cdev))

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

+246 −119

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/qlogic/qed/qed_init_ops.c

+57 −41

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/qlogic/qed/qed_init_ops.h

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn, 
			   size_t size);



#define STORE_RT_REG_AGG(hwfn, offset, val) \

	qed_init_store_rt_agg(hwfn, offset, (u32 *)&val, sizeof(val))

	qed_init_store_rt_agg(hwfn, offset, (u32 *)&(val), sizeof(val))



/**

 * qed_gtt_init(): Initialize GTT global windows and set admin window

drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

+10 −4
Original line number Diff line number Diff line
@@ -126,6 +126,8 @@ 
	0x1009c4UL

#define  QM_REG_PF_EN \

	0x2f2ea4UL

#define QM_REG_RLGLBLUPPERBOUND \

	0x2f3c00UL

#define TCFC_REG_WEAK_ENABLE_VF \

	0x2d0704UL

#define  TCFC_REG_STRONG_ENABLE_PF \
@@ -576,7 +578,7 @@ 
#define PRS_REG_ENCAPSULATION_TYPE_EN	0x1f0730UL

#define PRS_REG_GRE_PROTOCOL		0x1f0734UL

#define PRS_REG_VXLAN_PORT		0x1f0738UL

#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2	0x1f099cUL

#define PRS_REG_OUTPUT_FORMAT_4_0	0x1f099cUL

#define NIG_REG_ENC_TYPE_ENABLE		0x501058UL



#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE		(0x1 << 0)
@@ -595,8 +597,9 @@ 
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN		0x10090cUL

#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN		0x100910UL

#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN		0x100914UL

#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5		0x10092cUL

#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5	0x100930UL

#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2		0x10092cUL

#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2		0x100930UL





#define NIG_REG_NGE_IP_ENABLE			0x508b28UL

#define NIG_REG_NGE_ETH_ENABLE			0x508b2cUL
@@ -606,7 +609,10 @@ 


#define QM_REG_WFQPFWEIGHT	0x2f4e80UL

#define QM_REG_WFQVPWEIGHT	0x2fa000UL



#define QM_REG_WFQVPUPPERBOUND \

	0x2fb000UL

#define QM_REG_WFQVPCRD \

	0x2fc000UL

#define PGLCS_REG_DBG_SELECT_K2_E5 \

	0x001d14UL

#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \