Commit b965e6a4 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
Browse files

staging: comedi: ni_stc.h: tidy up NI_M_PLL_CTRL_REG bits 



Rename the CamelCase and convert the enum into defines. Use the BIT()
macro to define the bits.

Convert the inline functions MSeries_PLL_Divisor_Bits() and
MSeries_PLL_Multiplier_Bits() to macros. The helper function
ni_mseries_get_pll_parameters() always returns valid values for the
'divisor' and 'multiplier' so the sanity checking can safely be
removed.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 40aafd79

drivers/staging/comedi/drivers/ni_mio_common.c

+5 −9
Original line number Diff line number Diff line
@@ -4638,10 +4638,8 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, 
{

	unsigned div;

	unsigned best_div = 1;

	static const unsigned max_div = 0x10;

	unsigned mult;

	unsigned best_mult = 1;

	static const unsigned max_mult = 0x100;

	static const unsigned pico_per_nano = 1000;



	const unsigned reference_picosec = reference_period_ns * pico_per_nano;
@@ -4651,8 +4649,8 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, 
	static const unsigned fudge_factor_80_to_20Mhz = 4;

	int best_period_picosec = 0;



	for (div = 1; div <= max_div; ++div) {

		for (mult = 1; mult <= max_mult; ++mult) {

	for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {

		for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {

			unsigned new_period_ps =

			    (reference_picosec * div) / mult;

			if (abs(new_period_ps - target_picosec) <
@@ -4700,8 +4698,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, 
	devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;

	ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,

		      RTSI_Trig_Direction_Register);

	pll_control_bits =

	    MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;

	pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;

	devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |

				    NI_M_CLK_FOUT2_TIMEBASE3_PLL;

	devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
@@ -4736,9 +4733,8 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, 
	}



	ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);

	pll_control_bits |=

	    MSeries_PLL_Divisor_Bits(freq_divider) |

	    MSeries_PLL_Multiplier_Bits(freq_multiplier);

	pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |

			    NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);



	ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);

	devpriv->clock_source = source;

drivers/staging/comedi/drivers/ni_stc.h

+10 −28
Original line number Diff line number Diff line
@@ -980,6 +980,16 @@ static const struct comedi_lrange range_ni_E_ao_ext; 
#define NI_M_CLK_FOUT2_PLL_SRC_STAR	NI_M_CLK_FOUT2_PLL_SRC(0x14)

#define NI_M_CLK_FOUT2_PLL_SRC_PXI10	NI_M_CLK_FOUT2_PLL_SRC(0x1d)

#define NI_M_PLL_CTRL_REG		0x1c6

#define NI_M_PLL_CTRL_VCO_MODE(x)	(((x) & 0x3) << 13)

#define NI_M_PLL_CTRL_VCO_MODE_200_325MHZ NI_M_PLL_CTRL_VCO_MODE(0)

#define NI_M_PLL_CTRL_VCO_MODE_175_225MHZ NI_M_PLL_CTRL_VCO_MODE(1)

#define NI_M_PLL_CTRL_VCO_MODE_100_225MHZ NI_M_PLL_CTRL_VCO_MODE(2)

#define NI_M_PLL_CTRL_VCO_MODE_75_150MHZ  NI_M_PLL_CTRL_VCO_MODE(3)

#define NI_M_PLL_CTRL_ENA		BIT(12)

#define NI_M_PLL_MAX_DIVISOR		0x10

#define NI_M_PLL_CTRL_DIVISOR(x)	(((x) & 0xf) << 8)

#define NI_M_PLL_MAX_MULTIPLIER		0x100

#define NI_M_PLL_CTRL_MULTIPLIER(x)	(((x) & 0xff) << 0)

#define NI_M_PLL_STATUS_REG		0x1c8

#define NI_M_PFI_OUT_SEL_REG(x)		(0x1d0 + ((x) * 2))

#define NI_M_PFI_DI_REG			0x1dc
@@ -997,34 +1007,6 @@ static const struct comedi_lrange range_ni_E_ao_ext; 
#define NI_M_STATIC_AI_CTRL_REG(x)	((x) ? (0x260 + (x)) : 0x064)

#define NI_M_AO_REF_ATTENUATION_REG(x)	(0x264 + (x))



enum MSeries_PLL_Control_Bits {

	MSeries_PLL_Enable_Bit = 0x1000,

	MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,

	MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,

	MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,

	MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000,

};

static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor)

{

	static const unsigned max_divisor = 0x10;

	if (divisor < 1 || divisor > max_divisor) {

		pr_err("%s: bug, invalid divisor=%i\n", __func__, divisor);

		return 0;

	}

	return (divisor & 0xf) << 8;

}



static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier)

{

	static const unsigned max_multiplier = 0x100;

	if (multiplier < 1 || multiplier > max_multiplier) {

		pr_err("%s: bug, invalid multiplier=%i\n", __func__,

		       multiplier);

		return 0;

	}

	return multiplier & 0xff;

}



enum MSeries_PLL_Status {

	MSeries_PLL_Locked_Bit = 0x1

};