Commit b98ab70e authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Hardcode 45W Bounding Box for DCN2.1 Diags 



[WHY]
Currently construction of clock limits gets skipped for diags.
This logic would be useful to get tested in diags.

[HOW]
Copy existing states to clk_table such that update_bw_bounding_box
logic gets used to fill the table.

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5dff371a

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+36 −83
Original line number Diff line number Diff line
@@ -1393,8 +1393,6 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
	unsigned int i, closest_clk_lvl;

	int j;



	// Default clock levels are used for diags, which may lead to overclocking.

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {

	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;

	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;

	dcn2_1_soc.num_chans = bw_params->num_channels;
@@ -1431,49 +1429,10 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];

		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;

	}

	}



	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);

}



/* Temporary Place holder until we can get them from fuse */

static struct dpm_clocks dummy_clocks = {

		.DcfClocks = {

				{.Freq = 400, .Vol = 1},

				{.Freq = 483, .Vol = 1},

				{.Freq = 602, .Vol = 1},

				{.Freq = 738, .Vol = 1} },

		.SocClocks = {

				{.Freq = 300, .Vol = 1},

				{.Freq = 400, .Vol = 1},

				{.Freq = 400, .Vol = 1},

				{.Freq = 400, .Vol = 1} },

		.FClocks = {

				{.Freq = 400, .Vol = 1},

				{.Freq = 800, .Vol = 1},

				{.Freq = 1067, .Vol = 1},

				{.Freq = 1600, .Vol = 1} },

		.MemClocks = {

				{.Freq = 800, .Vol = 1},

				{.Freq = 1600, .Vol = 1},

				{.Freq = 1067, .Vol = 1},

				{.Freq = 1600, .Vol = 1} },



};



static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,

		struct pp_smu_wm_range_sets *ranges)

{

	return PP_SMU_RESULT_OK;

}



static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,

		struct dpm_clocks *clock_table)

{

	*clock_table = dummy_clocks;

	return PP_SMU_RESULT_OK;

}



static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)

{

	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
@@ -1481,17 +1440,11 @@ static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 
	if (!pp_smu)

		return pp_smu;



	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {

		pp_smu->ctx.ver = PP_SMU_VER_RN;

		pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;

		pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;

	} else {



	dm_pp_get_funcs(ctx, pp_smu);



	if (pp_smu->ctx.ver != PP_SMU_VER_RN)

		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));

	}





	return pp_smu;

}