Commit b9ac08b3 authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: dac: ti-dac7612: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: 977724d2 ("iio:dac:ti-dac7612: Add driver for Texas Instruments DAC7612")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ricardo Ribalda <ribalda@kernel.org>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-65-jic23@kernel.org
parent 3637c49e

drivers/iio/dac/ti-dac7612.c

+2 −2
Original line number Diff line number Diff line
@@ -31,10 +31,10 @@ struct dac7612 { 
	struct mutex lock;



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	uint8_t data[2] ____cacheline_aligned;

	uint8_t data[2] __aligned(IIO_DMA_MINALIGN);

};



static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val)