Commit ba9e7a4a authored by Stanley.Yang's avatar Stanley.Yang Committed by Alex Deucher
Browse files

drm/amdgpu: add new write field for soc21 



add new write field macro to handle soc21
registers with reg prefix

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fb1d6835

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+8 −0
Original line number Diff line number Diff line
@@ -45,6 +45,14 @@ 
				~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \

			      0, ip##_HWIP)



#define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val)        \

	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name,   \

			(__RREG32_SOC15_RLC__( \

					adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \

					0, ip##_HWIP) & \

					~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \

			0, ip##_HWIP)



#define RREG32_SOC15(ip, inst, reg) \

	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

			 0, ip##_HWIP)