Commit bb3ab81b authored by Mike Travis's avatar Mike Travis Committed by Borislav Petkov
Browse files

x86/platform/uv: Update TSC sync state for UV5 



The UV5 platform synchronizes the TSCs among all chassis, and will not
proceed to OS boot without achieving synchronization.  Previous UV
platforms provided a register indicating successful synchronization.
This is no longer available on UV5.  On this platform TSC_ADJUST
should not be reset by the kernel.

Signed-off-by: default avatarMike Travis <mike.travis@hpe.com>
Signed-off-by: default avatarSteve Wahl <steve.wahl@hpe.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarDimitri Sivanich <dimitri.sivanich@hpe.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com
parent d812f7c4

arch/x86/kernel/apic/x2apic_uv_x.c

+7 −1
Original line number Diff line number Diff line
@@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void) 
	int mmr_shift;

	char *state;



	/* Different returns from different UV BIOS versions */

	/* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */

	if (!is_uv(UV2|UV3|UV4)) {

		mark_tsc_async_resets("UV5+");

		return;

	}



	/* UV2,3,4, UV BIOS TSC sync state available */

	mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);

	mmr_shift =

		is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;