Commit bbf282d8 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add asic callback to get memsize register



Newer asics use different registers so abstract it.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c722865a
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -1221,6 +1221,8 @@ struct amdgpu_asic_funcs {
	/* static power management */
	int (*get_pcie_lanes)(struct amdgpu_device *adev);
	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
	/* get config memsize register */
	u32 (*get_config_memsize)(struct amdgpu_device *adev);
};

/*
@@ -1680,6 +1682,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
+1 −1
Original line number Diff line number Diff line
@@ -713,7 +713,7 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
		return true;
	}
	/* then check MEM_SIZE, in case the crtcs are off */
	reg = RREG32(mmCONFIG_MEMSIZE);
	reg = amdgpu_asic_get_config_memsize(adev);

	if (reg)
		return false;
+6 −0
Original line number Diff line number Diff line
@@ -1212,6 +1212,11 @@ static int cik_asic_reset(struct amdgpu_device *adev)
	return r;
}

static u32 cik_get_config_memsize(struct amdgpu_device *adev)
{
	return RREG32(mmCONFIG_MEMSIZE);
}

static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
			      u32 cntl_reg, u32 status_reg)
{
@@ -1641,6 +1646,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
	.get_xclk = &cik_get_xclk,
	.set_uvd_clocks = &cik_set_uvd_clocks,
	.set_vce_clocks = &cik_set_vce_clocks,
	.get_config_memsize = &cik_get_config_memsize,
};

static int cik_common_early_init(void *handle)
+7 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@
#include "gmc/gmc_6_0_d.h"
#include "dce/dce_6_0_d.h"
#include "uvd/uvd_4_0_d.h"
#include "bif/bif_3_0_d.h"

static const u32 tahiti_golden_registers[] =
{
@@ -1155,6 +1156,11 @@ static int si_asic_reset(struct amdgpu_device *adev)
	return 0;
}

static u32 si_get_config_memsize(struct amdgpu_device *adev)
{
	return RREG32(mmCONFIG_MEMSIZE);
}

static void si_vga_set_state(struct amdgpu_device *adev, bool state)
{
	uint32_t temp;
@@ -1206,6 +1212,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
	.get_xclk = &si_get_xclk,
	.set_uvd_clocks = &si_set_uvd_clocks,
	.set_vce_clocks = NULL,
	.get_config_memsize = &si_get_config_memsize,
};

static uint32_t si_get_rev_id(struct amdgpu_device *adev)
+6 −0
Original line number Diff line number Diff line
@@ -751,6 +751,11 @@ static int vi_asic_reset(struct amdgpu_device *adev)
	return r;
}

static u32 vi_get_config_memsize(struct amdgpu_device *adev)
{
	return RREG32(mmCONFIG_MEMSIZE);
}

static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
			u32 cntl_reg, u32 status_reg)
{
@@ -900,6 +905,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
	.get_xclk = &vi_get_xclk,
	.set_uvd_clocks = &vi_set_uvd_clocks,
	.set_vce_clocks = &vi_set_vce_clocks,
	.get_config_memsize = &vi_get_config_memsize,
};

static int vi_common_early_init(void *handle)