Commit bbfc59be authored Jun 01, 2020 by Peng Fan Committed by Shawn Guo Jun 23, 2020

arm64: dts: imx8m: add mu node



Add mu node to let A53 could communicate with M Core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

parent 12fa1078

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -775,6 +775,14 @@ uart4: serial@30a60000 {
	status = "disabled";		status = "disabled";
	};		};

			mu: mailbox@30aa0000 {
			compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
			reg = <0x30aa0000 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MM_CLK_MU_ROOT>;
			#mbox-cells = <2>;
			};

	usdhc1: mmc@30b40000 {		usdhc1: mmc@30b40000 {
	compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";		compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b40000 0x10000>;		reg = <0x30b40000 0x10000>;

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -675,6 +675,14 @@ uart4: serial@30a60000 {
	status = "disabled";		status = "disabled";
	};		};

			mu: mailbox@30aa0000 {
			compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
			reg = <0x30aa0000 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MN_CLK_MU_ROOT>;
			#mbox-cells = <2>;
			};

	usdhc1: mmc@30b40000 {		usdhc1: mmc@30b40000 {
	compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";		compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b40000 0x10000>;		reg = <0x30b40000 0x10000>;

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -627,6 +627,14 @@ uart4: serial@30a60000 {
	status = "disabled";		status = "disabled";
	};		};

			mu: mailbox@30aa0000 {
			compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
			reg = <0x30aa0000 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MP_CLK_MU_ROOT>;
			#mbox-cells = <2>;
			};

	i2c5: i2c@30ad0000 {		i2c5: i2c@30ad0000 {
	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";		compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;		#address-cells = <1>;

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -963,6 +963,14 @@ uart4: serial@30a60000 {
	status = "disabled";		status = "disabled";
	};		};

			mu: mailbox@30aa0000 {
			compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
			reg = <0x30aa0000 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
			#mbox-cells = <2>;
			};

	usdhc1: mmc@30b40000 {		usdhc1: mmc@30b40000 {
	compatible = "fsl,imx8mq-usdhc",		compatible = "fsl,imx8mq-usdhc",
	"fsl,imx7d-usdhc";		"fsl,imx7d-usdhc";