Commit bc74bf8f authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville
Browse files

ath9k: split ath9k_hw_btcoex_enable() into two helpers



One for 2-wire and another for 3-wire.

Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 75d7839f
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+37 −20
Original line number Diff line number Diff line
@@ -117,15 +117,19 @@ void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
	ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio);
}

void ath9k_hw_btcoex_enable(struct ath_hw *ah)
static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_info *btcoex_info = &ah->btcoex_info;

	if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
	/* Configure the desired GPIO port for TX_FRAME output */
	ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
	} else {
}

static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_info *btcoex_info = &ah->btcoex_info;

	/*
	 * Program coex mode and weight registers to
	 * enable coex 3-wire
@@ -134,15 +138,28 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah)
	REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_info->bt_coex_weights);
	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_info->bt_coex_mode2);

		REG_RMW_FIELD(ah, AR_QUIET1,
				AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
		REG_RMW_FIELD(ah, AR_PCU_MISC,
				AR_PCU_BT_ANT_PREVENT_RX, 0);
	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);

	ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
}

void ath9k_hw_btcoex_enable(struct ath_hw *ah)
{
	struct ath_btcoex_info *btcoex_info = &ah->btcoex_info;

	switch (btcoex_info->btcoex_scheme) {
	case ATH_BTCOEX_CFG_NONE:
		break;
	case ATH_BTCOEX_CFG_2WIRE:
		ath9k_hw_btcoex_enable_2wire(ah);
		break;
	case ATH_BTCOEX_CFG_3WIRE:
		ath9k_hw_btcoex_enable_3wire(ah);
		break;
	}

	REG_RMW(ah, AR_GPIO_PDPU,
		(0x2 << (btcoex_info->btactive_gpio * 2)),
		(0x3 << (btcoex_info->btactive_gpio * 2)));