Commit bc8e81a5 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v5.19-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.19

  - Add support for the new RZ/G2UL SoC,
  - Add drive-strength support for R-Car E3,
  - Add RPC/QSPI pin groups on R-Car E3 and E3,
  - Miscellaneous fixes and improvements.
parents a6a5c173 f7bc5f52

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+3 −2
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ maintainers: 
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO

  controller.

  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and

  GPIO controller.

  Pin multiplexing and GPIO configuration is performed on a per-pin basis.

  Each port features up to 8 pins, each of them configurable for GPIO function

  (port mode) or in alternate function mode.
@@ -23,6 +23,7 @@ properties: 
    oneOf:

      - items:

          - enum:

              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}

              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}



      - items:

drivers/pinctrl/renesas/Kconfig

+3 −4
Original line number Diff line number Diff line
@@ -38,8 +38,7 @@ config PINCTRL_RENESAS 
	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995

	select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0

	select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0

	select PINCTRL_RZG2L if ARCH_R9A07G044

	select PINCTRL_RZG2L if ARCH_R9A07G054

	select PINCTRL_RZG2L if ARCH_RZG2L

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -184,14 +183,14 @@ config PINCTRL_RZA2 
	  This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.



config PINCTRL_RZG2L

	bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST

	bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST

	depends on OF

	select GPIOLIB

	select GENERIC_PINCTRL_GROUPS

	select GENERIC_PINMUX_FUNCTIONS

	select GENERIC_PINCONF

	help

	  This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}

	  This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L}

	  platforms.



config PINCTRL_PFC_R8A77470

drivers/pinctrl/renesas/core.c

+36 −31
Original line number Diff line number Diff line
@@ -1007,7 +1007,18 @@ static void __init sh_pfc_compare_groups(const char *drvname, 
static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)

{

	const struct pinmux_drive_reg *drive_regs = info->drive_regs;

#define drive_nfields	ARRAY_SIZE(drive_regs->fields)

#define drive_ofs(i)	drive_regs[(i) / drive_nfields]

#define drive_reg(i)	drive_ofs(i).reg

#define drive_bit(i)	((i) % drive_nfields)

#define drive_field(i)	drive_ofs(i).fields[drive_bit(i)]

	const struct pinmux_bias_reg *bias_regs = info->bias_regs;

#define bias_npins	ARRAY_SIZE(bias_regs->pins)

#define bias_ofs(i)	bias_regs[(i) / bias_npins]

#define bias_puen(i)	bias_ofs(i).puen

#define bias_pud(i)	bias_ofs(i).pud

#define bias_bit(i)	((i) % bias_npins)

#define bias_pin(i)	bias_ofs(i).pins[bias_bit(i)]

	const char *drvname = info->name;

	unsigned int *refcnts;

	unsigned int i, j, k;
@@ -1076,17 +1087,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) 
			if (!drive_regs) {

				sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");

			} else {

				for (j = 0; drive_regs[j / 8].reg; j++) {

					if (!drive_regs[j / 8].fields[j % 8].pin &&

					    !drive_regs[j / 8].fields[j % 8].offset &&

					    !drive_regs[j / 8].fields[j % 8].size)

				for (j = 0; drive_reg(j); j++) {

					if (!drive_field(j).pin &&

					    !drive_field(j).offset &&

					    !drive_field(j).size)

						continue;



					if (drive_regs[j / 8].fields[j % 8].pin == pin->pin)

					if (drive_field(j).pin == pin->pin)

						break;

				}



				if (!drive_regs[j / 8].reg)

				if (!drive_reg(j))

					sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",

						   pin->name);

			}
@@ -1164,20 +1175,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) 
	for (i = 0; drive_regs && drive_regs[i].reg; i++)

		sh_pfc_check_drive_reg(info, &drive_regs[i]);



	for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) {

		if (!drive_regs[i / 8].fields[i % 8].pin &&

		    !drive_regs[i / 8].fields[i % 8].offset &&

		    !drive_regs[i / 8].fields[i % 8].size)

	for (i = 0; drive_regs && drive_reg(i); i++) {

		if (!drive_field(i).pin && !drive_field(i).offset &&

		    !drive_field(i).size)

			continue;



		for (j = 0; j < i; j++) {

			if (drive_regs[i / 8].fields[i % 8].pin ==

			    drive_regs[j / 8].fields[j % 8].pin &&

			    drive_regs[j / 8].fields[j % 8].offset &&

			    drive_regs[j / 8].fields[j % 8].size) {

				sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n",

					   drive_regs[i / 8].reg, i % 8,

					   drive_regs[j / 8].reg, j % 8);

			if (drive_field(i).pin == drive_field(j).pin &&

			    drive_field(j).offset && drive_field(j).size) {

				sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",

					   drive_reg(i), drive_bit(i),

					   drive_reg(j), drive_bit(j));

			}

		}

	}
@@ -1186,26 +1194,23 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) 
	for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)

		sh_pfc_check_bias_reg(info, &bias_regs[i]);



	for (i = 0; bias_regs &&

		    (bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) {

		if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)

	for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {

		if (bias_pin(i) == SH_PFC_PIN_NONE)

			continue;



		for (j = 0; j < i; j++) {

			if (bias_regs[i / 32].pins[i % 32] !=

			    bias_regs[j / 32].pins[j % 32])

			if (bias_pin(i) != bias_pin(j))

				continue;



			if (bias_regs[i / 32].puen && bias_regs[j / 32].puen)

				sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",

					   bias_regs[i / 32].puen, i % 32,

					   bias_regs[j / 32].puen, j % 32);

			if (bias_regs[i / 32].pud && bias_regs[j / 32].pud)

				sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",

					   bias_regs[i / 32].pud, i % 32,

					   bias_regs[j / 32].pud, j % 32);

			if (bias_puen(i) && bias_puen(j))

				sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",

					   bias_puen(i), bias_bit(i),

					   bias_puen(j), bias_bit(j));

			if (bias_pud(i) && bias_pud(j))

				sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",

					   bias_pud(i), bias_bit(i),

					   bias_pud(j), bias_bit(j));

		}



	}



	/* Check ioctrl registers */

drivers/pinctrl/renesas/gpio.c

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 


#include <linux/device.h>

#include <linux/gpio/driver.h>

#include <linux/init.h>

#include <linux/module.h>

#include <linux/pinctrl/consumer.h>

#include <linux/slab.h>

drivers/pinctrl/renesas/pfc-emev2.c

+0 −1
Original line number Diff line number Diff line
@@ -4,7 +4,6 @@ 
 *

 * Copyright (C) 2015 Niklas Söderlund

 */

#include <linux/init.h>

#include <linux/kernel.h>



#include "sh_pfc.h"