Commit bd1b5799 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Add PMFW headers for SMU 13.0.6 



Initial version of PMFW interface and message
headers for SMU 13.0.6 support.

v2: squash in location fixes (Alex)
v3: squash in updates (Alex)

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3e22193d

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

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/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef SMU_13_0_6_DRIVER_IF_H

#define SMU_13_0_6_DRIVER_IF_H



// *** IMPORTANT ***

// PMFW TEAM: Always increment the interface version if

// anything is changed in this file

#define SMU13_0_6_DRIVER_IF_VERSION 0x08042022



//I2C Interface

#define NUM_I2C_CONTROLLERS                8

#define I2C_CONTROLLER_ENABLED             1

#define I2C_CONTROLLER_DISABLED            0



#define MAX_SW_I2C_COMMANDS                24



typedef enum {

  I2C_CONTROLLER_PORT_0, //CKSVII2C0

  I2C_CONTROLLER_PORT_1, //CKSVII2C1

  I2C_CONTROLLER_PORT_COUNT,

} I2cControllerPort_e;



typedef enum {

  UNSUPPORTED_1,              //50  Kbits/s not supported anymore!

  I2C_SPEED_STANDARD_100K,    //100 Kbits/s

  I2C_SPEED_FAST_400K,        //400 Kbits/s

  I2C_SPEED_FAST_PLUS_1M,     //1   Mbits/s (in fast mode)

  UNSUPPORTED_2,              //1   Mbits/s (in high speed mode)  not supported anymore!

  UNSUPPORTED_3,              //2.3 Mbits/s  not supported anymore!

  I2C_SPEED_COUNT,

} I2cSpeed_e;



typedef enum {

  I2C_CMD_READ,

  I2C_CMD_WRITE,

  I2C_CMD_COUNT,

} I2cCmdType_e;



#define CMDCONFIG_STOP_BIT             0

#define CMDCONFIG_RESTART_BIT          1

#define CMDCONFIG_READWRITE_BIT        2 //bit should be 0 for read, 1 for write



#define CMDCONFIG_STOP_MASK           (1 << CMDCONFIG_STOP_BIT)

#define CMDCONFIG_RESTART_MASK        (1 << CMDCONFIG_RESTART_BIT)

#define CMDCONFIG_READWRITE_MASK      (1 << CMDCONFIG_READWRITE_BIT)



typedef struct {

  uint8_t ReadWriteData;  //Return data for read. Data to send for write

  uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

} SwI2cCmd_t; //SW I2C Command Table



typedef struct {

  uint8_t    I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

  uint8_t    I2CSpeed;          //Use I2cSpeed_e to indicate speed to select

  uint8_t    SlaveAddress;      //Slave address of device

  uint8_t    NumCmds;           //Number of commands

  SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];

} SwI2cRequest_t; // SW I2C Request Table



typedef struct {

  SwI2cRequest_t SwI2cRequest;

  uint32_t       Spare[8];

  uint32_t       MmHubPadding[8]; // SMU internal use

} SwI2cRequestExternal_t;



typedef enum {

  PPCLK_VCLK,

  PPCLK_DCLK,

  PPCLK_SOCCLK,

  PPCLK_UCLK,

  PPCLK_FCLK,

  PPCLK_LCLK,

  PPCLK_COUNT,

} PPCLK_e;



typedef enum {

  GPIO_INT_POLARITY_ACTIVE_LOW,

  GPIO_INT_POLARITY_ACTIVE_HIGH,

} GpioIntPolarity_e;



//TODO confirm if this is used in SMU_13_0_6 PPSMC_MSG_SetUclkDpmMode

typedef enum {

  UCLK_DPM_MODE_BANDWIDTH,

  UCLK_DPM_MODE_LATENCY,

} UCLK_DPM_MODE_e;



typedef struct {

  //0-26 SOC, 27-29 SOCIO

  uint16_t avgPsmCount[30];

  uint16_t minPsmCount[30];

  float    avgPsmVoltage[30];

  float    minPsmVoltage[30];

} AvfsDebugTableAid_t;



typedef struct {

  //0-27 GFX, 28-29 SOC

  uint16_t avgPsmCount[30];

  uint16_t minPsmCount[30];

  float    avgPsmVoltage[30];

  float    minPsmVoltage[30];

} AvfsDebugTableXcd_t;



// These defines are used with the following messages:

// SMC_MSG_TransferTableDram2Smu

// SMC_MSG_TransferTableSmu2Dram

// #define TABLE_PPTABLE                 0

// #define TABLE_AVFS_PSM_DEBUG          1

// #define TABLE_AVFS_FUSE_OVERRIDE      2

// #define TABLE_PMSTATUSLOG             3

// #define TABLE_SMU_METRICS             4

// #define TABLE_DRIVER_SMU_CONFIG       5

// #define TABLE_I2C_COMMANDS            6

// #define TABLE_COUNT                   7



// // Table transfer status

// #define TABLE_TRANSFER_OK         0x0

// #define TABLE_TRANSFER_FAILED     0xFF

// #define TABLE_TRANSFER_PENDING    0xAB



#endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

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/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef SMU_13_0_6_PMFW_H

#define SMU_13_0_6_PMFW_H



#define NUM_VCLK_DPM_LEVELS   4

#define NUM_DCLK_DPM_LEVELS   4

#define NUM_SOCCLK_DPM_LEVELS 4

#define NUM_LCLK_DPM_LEVELS   4

#define NUM_UCLK_DPM_LEVELS   4

#define NUM_FCLK_DPM_LEVELS   4

#define NUM_XGMI_DPM_LEVELS   2

#define NUM_CXL_BITRATES      4

#define NUM_PCIE_BITRATES     4

#define NUM_XGMI_BITRATES     4

#define NUM_XGMI_WIDTHS       3



typedef enum {

/*0*/   FEATURE_DATA_CALCULATION            = 0,

/*1*/   FEATURE_DPM_CCLK                    = 1,

/*2*/   FEATURE_DPM_FCLK                    = 2,

/*3*/   FEATURE_DPM_GFXCLK                  = 3,

/*4*/   FEATURE_DPM_LCLK                    = 4,

/*5*/   FEATURE_DPM_SOCCLK                  = 5,

/*6*/   FEATURE_DPM_UCLK                    = 6,

/*7*/   FEATURE_DPM_VCN                     = 7,

/*8*/   FEATURE_DPM_XGMI                    = 8,

/*9*/   FEATURE_DS_FCLK                     = 9,

/*10*/  FEATURE_DS_GFXCLK                   = 10,

/*11*/  FEATURE_DS_LCLK                     = 11,

/*12*/  FEATURE_DS_MP0CLK                   = 12,

/*13*/  FEATURE_DS_MP1CLK                   = 13,

/*14*/  FEATURE_DS_MPIOCLK                  = 14,

/*15*/  FEATURE_DS_SOCCLK                   = 15,

/*16*/  FEATURE_DS_VCN                      = 16,

/*17*/  FEATURE_APCC_DFLL                   = 17,

/*18*/  FEATURE_APCC_PLUS                   = 18,

/*19*/  FEATURE_DF_CSTATE                   = 19,

/*20*/  FEATURE_CC6                         = 20,

/*21*/  FEATURE_PC6                         = 21,

/*22*/  FEATURE_CPPC                        = 22,

/*23*/  FEATURE_PPT                         = 23,

/*24*/  FEATURE_TDC                         = 24,

/*25*/  FEATURE_THERMAL                     = 25,

/*26*/  FEATURE_SOC_PCC                     = 26,

/*27*/  FEATURE_CCD_PCC                     = 27,

/*28*/  FEATURE_CCD_EDC                     = 28,

/*29*/  FEATURE_PROCHOT                     = 29,

/*30*/  FEATURE_DVO_CCLK                    = 30,

/*31*/  FEATURE_FDD_AID_HBM                 = 31,

/*32*/  FEATURE_FDD_AID_SOC                 = 32,

/*33*/  FEATURE_FDD_XCD_EDC                 = 33,

/*34*/  FEATURE_FDD_XCD_XVMIN               = 34,

/*35*/  FEATURE_FW_CTF                      = 35,

/*36*/  FEATURE_GFXOFF                      = 36,

/*37*/  FEATURE_SMU_CG                      = 37,

/*38*/  FEATURE_PSI7                        = 38,

/*39*/  FEATURE_CSTATE_BOOST                = 39,

/*40*/  FEATURE_XGMI_PER_LINK_PWR_DOWN      = 40,

/*41*/  FEATURE_CXL_QOS                     = 41,

/*42*/  FEATURE_SOC_DC_RTC                  = 42,

/*43*/  FEATURE_GFX_DC_RTC                  = 43,



/*44*/  NUM_FEATURES                        = 44

} FEATURE_LIST_e;



//enum for MPIO PCIe gen speed msgs

typedef enum {

  PCIE_LINK_SPEED_INDEX_TABLE_GEN1,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN2,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN3,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN4,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN5,

  PCIE_LINK_SPEED_INDEX_TABLE_COUNT

} PCIE_LINK_SPEED_INDEX_TABLE_e;



typedef enum {

  VOLTAGE_COLD_0,

  VOLTAGE_COLD_1,

  VOLTAGE_COLD_2,

  VOLTAGE_COLD_3,

  VOLTAGE_COLD_4,

  VOLTAGE_COLD_5,

  VOLTAGE_COLD_6,

  VOLTAGE_COLD_7,

  VOLTAGE_MID_0,

  VOLTAGE_MID_1,

  VOLTAGE_MID_2,

  VOLTAGE_MID_3,

  VOLTAGE_MID_4,

  VOLTAGE_MID_5,

  VOLTAGE_MID_6,

  VOLTAGE_MID_7,

  VOLTAGE_HOT_0,

  VOLTAGE_HOT_1,

  VOLTAGE_HOT_2,

  VOLTAGE_HOT_3,

  VOLTAGE_HOT_4,

  VOLTAGE_HOT_5,

  VOLTAGE_HOT_6,

  VOLTAGE_HOT_7,

  VOLTAGE_GUARDBAND_COUNT

} GFX_GUARDBAND_e;



#define SMU_METRICS_TABLE_VERSION 0x1



typedef struct {

  uint32_t AccumulationCounter;



  //TEMPERATURE

  uint32_t MaxSocketTemperature;

  uint32_t MaxVrTemperature;

  uint32_t MaxHbmTemperature;

  uint64_t MaxSocketTemperatureAcc;

  uint64_t MaxVrTemperatureAcc;

  uint64_t MaxHbmTemperatureAcc;



  //POWER

  uint32_t SocketPowerLimit;

  uint32_t MaxSocketPowerLimit;

  uint32_t SocketPower;



  //ENERGY

  uint64_t Timestamp;

  uint64_t SocketEnergyAcc;

  uint64_t CcdEnergyAcc;

  uint64_t XcdEnergyAcc;

  uint64_t AidEnergyAcc;

  uint64_t HbmEnergyAcc;



  //FREQUENCY

  uint32_t CclkFrequencyLimit;

  uint32_t GfxclkFrequencyLimit;

  uint32_t FclkFrequency;

  uint32_t UclkFrequency;

  uint32_t SocclkFrequency[4];

  uint32_t VclkFrequency[4];

  uint32_t DclkFrequency[4];

  uint32_t LclkFrequency[4];

  uint64_t GfxclkFrequencyAcc[8];

  uint64_t CclkFrequencyAcc[96];



  //FREQUENCY RANGE

  uint32_t MaxCclkFrequency;

  uint32_t MinCclkFrequency;

  uint32_t MaxGfxclkFrequency;

  uint32_t MinGfxclkFrequency;

  uint32_t FclkFrequencyTable[4];

  uint32_t UclkFrequencyTable[4];

  uint32_t SocclkFrequencyTable[4];

  uint32_t VclkFrequencyTable[4];

  uint32_t DclkFrequencyTable[4];

  uint32_t LclkFrequencyTable[4];

  uint32_t MaxLclkDpmRange;

  uint32_t MinLclkDpmRange;



  //XGMI

  uint32_t XgmiWidth;

  uint32_t XgmiBitrate;

  uint64_t XgmiReadBandwidthAcc[8];

  uint64_t XgmiWriteBandwidthAcc[8];



  //ACTIVITY

  uint32_t SocketC0Residency;

  uint32_t SocketGfxBusy;

  uint32_t DramBandwidthUtilization;

  uint64_t SocketC0ResidencyAcc;

  uint64_t SocketGfxBusyAcc;

  uint64_t DramBandwidthAcc;

  uint32_t MaxDramBandwidth;

  uint64_t DramBandwidthUtilizationAcc;

  uint64_t PcieBandwidthAcc[4];



  //THROTTLERS

  uint32_t ProchotResidencyAcc;

  uint32_t PptResidencyAcc;

  uint32_t SocketThmResidencyAcc;

  uint32_t VrThmResidencyAcc;

  uint32_t HbmThmResidencyAcc;

} MetricsTable_t;



#define SMU_VF_METRICS_TABLE_VERSION 0x1



typedef struct {

  uint32_t AccumulationCounter;

  uint32_t InstGfxclk_TargFreq;

  uint64_t AccGfxclk_TargFreq;

  uint64_t AccGfxRsmuDpm_Busy;

} VfMetricsTable_t;



#endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h

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/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef SMU_13_0_6_PPSMC_H

#define SMU_13_0_6_PPSMC_H



// SMU Response Codes:

#define PPSMC_Result_OK                             0x1

#define PPSMC_Result_Failed                         0xFF

#define PPSMC_Result_UnknownCmd                     0xFE

#define PPSMC_Result_CmdRejectedPrereq              0xFD

#define PPSMC_Result_CmdRejectedBusy                0xFC



// Message Definitions:

#define PPSMC_MSG_TestMessage                       0x1

#define PPSMC_MSG_GetSmuVersion                     0x2

#define PPSMC_MSG_GfxDriverReset                    0x3

#define PPSMC_MSG_GetDriverIfVersion                0x4

#define PPSMC_MSG_EnableAllSmuFeatures              0x5

#define PPSMC_MSG_DisableAllSmuFeatures             0x6

#define PPSMC_MSG_RequestI2cTransaction             0x7

#define PPSMC_MSG_GetMetricsVersion                 0x8

#define PPSMC_MSG_GetMetricsTable                   0x9

#define PPSMC_MSG_GetEccInfoTable                   0xA

#define PPSMC_MSG_GetEnabledSmuFeaturesLow          0xB

#define PPSMC_MSG_GetEnabledSmuFeaturesHigh         0xC

#define PPSMC_MSG_SetDriverDramAddrHigh             0xD

#define PPSMC_MSG_SetDriverDramAddrLow              0xE

#define PPSMC_MSG_SetToolsDramAddrHigh              0xF

#define PPSMC_MSG_SetToolsDramAddrLow               0x10

#define PPSMC_MSG_SetSystemVirtualDramAddrHigh      0x11

#define PPSMC_MSG_SetSystemVirtualDramAddrLow       0x12

#define PPSMC_MSG_SetSoftMinByFreq                  0x13

#define PPSMC_MSG_SetSoftMaxByFreq                  0x14

#define PPSMC_MSG_GetMinDpmFreq                     0x15

#define PPSMC_MSG_GetMaxDpmFreq                     0x16

#define PPSMC_MSG_GetDpmFreqByIndex                 0x17

#define PPSMC_MSG_SetPptLimit                       0x18

#define PPSMC_MSG_GetPptLimit                       0x19

#define PPSMC_MSG_DramLogSetDramAddrHigh            0x1A

#define PPSMC_MSG_DramLogSetDramAddrLow             0x1B

#define PPSMC_MSG_DramLogSetDramSize                0x1C

#define PPSMC_MSG_GetDebugData                      0x1D

#define PPSMC_MSG_HeavySBR                          0x1E

#define PPSMC_MSG_SetNumBadHbmPagesRetired          0x1F

#define PPSMC_MSG_DFCstateControl                   0x20

#define PPSMC_MSG_GetGmiPwrDnHyst                   0x21

#define PPSMC_MSG_SetGmiPwrDnHyst                   0x22

#define PPSMC_MSG_GmiPwrDnControl                   0x23

#define PPSMC_MSG_EnterGfxoff                       0x24

#define PPSMC_MSG_ExitGfxoff                        0x25

#define PPSMC_MSG_EnableDeterminism                 0x26

#define PPSMC_MSG_DisableDeterminism                0x27

#define PPSMC_MSG_DumpSTBtoDram                     0x28

#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh       0x29

#define PPSMC_MSG_STBtoDramLogSetDramAddrLow        0x2A

#define PPSMC_MSG_STBtoDramLogSetDramSize           0x2B

#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x2C

#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow  0x2D

#define PPSMC_MSG_GfxDriverResetRecovery            0x2E

#define PPSMC_MSG_TriggerVFFLR                      0x2F

#define PPSMC_MSG_SetSoftMinGfxClk                  0x30

#define PPSMC_MSG_SetSoftMaxGfxClk                  0x31

#define PPSMC_MSG_GetMinGfxDpmFreq                  0x32

#define PPSMC_MSG_GetMaxGfxDpmFreq                  0x33

#define PPSMC_Message_Count                         0x34



//PPSMC Reset Types for driver msg argument

#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET        0x1

#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET	      0x2

#define PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET        0x3



typedef uint32_t PPSMC_Result;

typedef uint32_t PPSMC_MSG;



#endif