Commit bd70563f authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/dma: convert to new-style nvkm_engine 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 14d74aca

drivers/gpu/drm/nouveau/include/nvif/class.h

+5 −5
Original line number Diff line number Diff line
@@ -251,13 +251,13 @@ struct gf100_dma_v0 { 
	__u8  pad03[5];

};



struct gf110_dma_v0 {

struct gf119_dma_v0 {

	__u8  version;

#define GF110_DMA_V0_PAGE_LP                                               0x00

#define GF110_DMA_V0_PAGE_SP                                               0x01

#define GF119_DMA_V0_PAGE_LP                                               0x00

#define GF119_DMA_V0_PAGE_SP                                               0x01

	__u8  page;

#define GF110_DMA_V0_KIND_PITCH                                            0x00

#define GF110_DMA_V0_KIND_VM                                               0xff

#define GF119_DMA_V0_KIND_PITCH                                            0x00

#define GF119_DMA_V0_KIND_VM                                               0xff

	__u8  kind;

	__u8  pad03[5];

};

drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h

+5 −10
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
#define __NVKM_DMA_H__

#include <core/engine.h>

struct nvkm_client;

struct nvkm_gpuobj;



struct nvkm_dmaobj {

	const struct nvkm_dmaobj_func *func;
@@ -18,20 +17,16 @@ struct nvkm_dmaobj { 
	u64 handle; /*XXX HANDLE MERGE */

};



struct nvkm_dmaobj_func {

	int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align,

		    struct nvkm_gpuobj **);

};



struct nvkm_dma {

	const struct nvkm_dma_func *func;

	struct nvkm_engine engine;

};



struct nvkm_dmaobj *

nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object);



extern struct nvkm_oclass *nv04_dmaeng_oclass;

extern struct nvkm_oclass *nv50_dmaeng_oclass;

extern struct nvkm_oclass *gf100_dmaeng_oclass;

extern struct nvkm_oclass *gf110_dmaeng_oclass;

int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **);

int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **);

int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **);

int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **);

#endif

drivers/gpu/drm/nouveau/nv50_display.c

+4 −4
Original line number Diff line number Diff line
@@ -2339,7 +2339,7 @@ nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kin 
		union {

			struct nv50_dma_v0 nv50;

			struct gf100_dma_v0 gf100;

			struct gf110_dma_v0 gf110;

			struct gf119_dma_v0 gf119;

		};

	} args = {};

	struct nv50_fbdma *fbdma;
@@ -2375,9 +2375,9 @@ nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kin 
		args.gf100.kind = kind;

		size += sizeof(args.gf100);

	} else {

		args.gf110.page = GF110_DMA_V0_PAGE_LP;

		args.gf110.kind = kind;

		size += sizeof(args.gf110);

		args.gf119.page = GF119_DMA_V0_PAGE_LP;

		args.gf119.kind = kind;

		size += sizeof(args.gf119);

	}



	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+69 −69
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ nv4_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv04_fifo_new,

//	.gr = nv04_gr_new,

//	.sw = nv04_sw_new,
@@ -107,7 +107,7 @@ nv5_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv04_fifo_new,

//	.gr = nv04_gr_new,

//	.sw = nv04_sw_new,
@@ -128,7 +128,7 @@ nv10_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.gr = nv10_gr_new,

};
@@ -147,7 +147,7 @@ nv11_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv10_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,
@@ -168,7 +168,7 @@ nv15_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv10_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,
@@ -189,7 +189,7 @@ nv17_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,
@@ -210,7 +210,7 @@ nv18_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,
@@ -231,7 +231,7 @@ nv1a_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv10_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,
@@ -252,7 +252,7 @@ nv1f_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,
@@ -273,7 +273,7 @@ nv20_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv20_gr_new,

//	.sw = nv10_sw_new,
@@ -294,7 +294,7 @@ nv25_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv25_gr_new,

//	.sw = nv10_sw_new,
@@ -315,7 +315,7 @@ nv28_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv25_gr_new,

//	.sw = nv10_sw_new,
@@ -336,7 +336,7 @@ nv2a_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv2a_gr_new,

//	.sw = nv10_sw_new,
@@ -357,7 +357,7 @@ nv30_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv30_gr_new,

//	.sw = nv10_sw_new,
@@ -378,7 +378,7 @@ nv31_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv30_gr_new,

//	.mpeg = nv31_mpeg_new,
@@ -400,7 +400,7 @@ nv34_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv34_gr_new,

//	.mpeg = nv31_mpeg_new,
@@ -422,7 +422,7 @@ nv35_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv35_gr_new,

//	.sw = nv10_sw_new,
@@ -443,7 +443,7 @@ nv36_chipset = { 
	.mmu = nv04_mmu_new,

	.timer = nv04_timer_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

//	.gr = nv35_gr_new,

//	.mpeg = nv31_mpeg_new,
@@ -467,7 +467,7 @@ nv40_chipset = { 
	.timer = nv40_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,
@@ -492,7 +492,7 @@ nv41_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,
@@ -517,7 +517,7 @@ nv42_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,
@@ -542,7 +542,7 @@ nv43_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,
@@ -567,7 +567,7 @@ nv44_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -592,7 +592,7 @@ nv45_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -617,7 +617,7 @@ nv46_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -642,7 +642,7 @@ nv47_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -667,7 +667,7 @@ nv49_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -692,7 +692,7 @@ nv4a_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -717,7 +717,7 @@ nv4b_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -742,7 +742,7 @@ nv4c_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -767,7 +767,7 @@ nv4e_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -795,7 +795,7 @@ nv50_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv50_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = nv50_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = nv50_mpeg_new,
@@ -820,7 +820,7 @@ nv63_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -845,7 +845,7 @@ nv67_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -870,7 +870,7 @@ nv68_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,

//	.dma = nv04_dma_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,
@@ -900,7 +900,7 @@ nv84_chipset = { 
	.bsp = g84_bsp_new,

	.cipher = g84_cipher_new,

//	.disp = g84_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -931,7 +931,7 @@ nv86_chipset = { 
	.bsp = g84_bsp_new,

	.cipher = g84_cipher_new,

//	.disp = g84_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -962,7 +962,7 @@ nv92_chipset = { 
	.bsp = g84_bsp_new,

	.cipher = g84_cipher_new,

//	.disp = g84_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -993,7 +993,7 @@ nv94_chipset = { 
	.bsp = g84_bsp_new,

	.cipher = g84_cipher_new,

//	.disp = g94_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -1021,7 +1021,7 @@ nv96_chipset = { 
	.mmu = nv50_mmu_new,

	.bar = g84_bar_new,

	.volt = nv40_volt_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.sw = nv50_sw_new,

//	.gr = nv50_gr_new,
@@ -1052,7 +1052,7 @@ nv98_chipset = { 
	.mmu = nv50_mmu_new,

	.bar = g84_bar_new,

	.volt = nv40_volt_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.sw = nv50_sw_new,

//	.gr = nv50_gr_new,
@@ -1086,7 +1086,7 @@ nva0_chipset = { 
	.bsp = g84_bsp_new,

	.cipher = g84_cipher_new,

//	.disp = gt200_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -1117,7 +1117,7 @@ nva3_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gt215_ce_new,

//	.disp = gt215_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -1150,7 +1150,7 @@ nva5_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gt215_ce_new,

//	.disp = gt215_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = gt215_mspdec_new,
@@ -1182,7 +1182,7 @@ nva8_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gt215_ce_new,

//	.disp = gt215_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = gt215_mspdec_new,
@@ -1212,7 +1212,7 @@ nvaa_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = g94_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = g98_mspdec_new,
@@ -1243,7 +1243,7 @@ nvac_chipset = { 
	.timer = nv41_timer_new,

	.volt = nv40_volt_new,

//	.disp = g94_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = g98_mspdec_new,
@@ -1276,7 +1276,7 @@ nvaf_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gt215_ce_new,

//	.disp = gt215_disp_new,

//	.dma = nv50_dma_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = gt215_mspdec_new,
@@ -1311,7 +1311,7 @@ nvc0_chipset = { 
	.ce[0] = gf100_ce_new,

	.ce[1] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf100_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1345,7 +1345,7 @@ nvc1_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf108_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1379,7 +1379,7 @@ nvc3_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1414,7 +1414,7 @@ nvc4_chipset = { 
	.ce[0] = gf100_ce_new,

	.ce[1] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1449,7 +1449,7 @@ nvc8_chipset = { 
	.ce[0] = gf100_ce_new,

	.ce[1] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf110_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1484,7 +1484,7 @@ nvce_chipset = { 
	.ce[0] = gf100_ce_new,

	.ce[1] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1518,7 +1518,7 @@ nvcf_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gf100_ce_new,

//	.disp = gt215_disp_new,

//	.dma = gf100_dma_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1550,7 +1550,7 @@ nvd7_chipset = { 
	.timer = nv41_timer_new,

	.ce[0] = gf100_ce_new,

//	.disp = gf119_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf117_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1584,7 +1584,7 @@ nvd9_chipset = { 
	.volt = nv40_volt_new,

	.ce[0] = gf100_ce_new,

//	.disp = gf119_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gf100_fifo_new,

//	.gr = gf119_gr_new,

	.mspdec = gf100_mspdec_new,
@@ -1620,7 +1620,7 @@ nve4_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk104_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

//	.gr = gk104_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1656,7 +1656,7 @@ nve6_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk104_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

//	.gr = gk104_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1692,7 +1692,7 @@ nve7_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk104_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

//	.gr = gk104_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1719,7 +1719,7 @@ nvea_chipset = { 
	.timer = gk20a_timer_new,

	.volt = gk20a_volt_new,

	.ce[2] = gk104_ce_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk20a_fifo_new,

//	.gr = gk20a_gr_new,

//	.pm = gk104_pm_new,
@@ -1752,7 +1752,7 @@ nvf0_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk110_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

//	.gr = gk110_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1788,7 +1788,7 @@ nvf1_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk110_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

//	.gr = gk110b_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1824,7 +1824,7 @@ nv106_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk110_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk208_fifo_new,

//	.gr = gk208_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1859,7 +1859,7 @@ nv108_chipset = { 
	.ce[1] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gk110_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk208_fifo_new,

//	.gr = gk208_gr_new,

	.mspdec = gk104_mspdec_new,
@@ -1892,7 +1892,7 @@ nv117_chipset = { 
	.ce[0] = gk104_ce_new,

	.ce[2] = gk104_ce_new,

//	.disp = gm107_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gk208_fifo_new,

//	.gr = gm107_gr_new,

//	.sw = gf100_sw_new,
@@ -1921,7 +1921,7 @@ nv124_chipset = { 
	.ce[1] = gm204_ce_new,

	.ce[2] = gm204_ce_new,

//	.disp = gm204_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gm204_fifo_new,

//	.gr = gm204_gr_new,

//	.sw = gf100_sw_new,
@@ -1950,7 +1950,7 @@ nv126_chipset = { 
	.ce[1] = gm204_ce_new,

	.ce[2] = gm204_ce_new,

//	.disp = gm204_disp_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gm204_fifo_new,

//	.gr = gm206_gr_new,

//	.sw = gf100_sw_new,
@@ -1971,7 +1971,7 @@ nv12b_chipset = { 
	.mmu = gf100_mmu_new,

	.timer = gk20a_timer_new,

	.ce[2] = gm204_ce_new,

//	.dma = gf119_dma_new,

	.dma = gf119_dma_new,

//	.fifo = gm20b_fifo_new,

//	.gr = gm20b_gr_new,

//	.sw = gf100_sw_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device) 
{

	switch (device->chipset) {

	case 0xc0:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;
@@ -36,7 +35,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc4:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
@@ -44,7 +42,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc3:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
@@ -52,7 +49,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xce:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
@@ -60,7 +56,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xcf:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
@@ -68,7 +63,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc1:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;
@@ -76,7 +70,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf108_pm_oclass;

		break;

	case 0xc8:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;
@@ -84,7 +77,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xd9:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;
@@ -92,7 +84,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;

		break;

	case 0xd7:

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;