Commit bdd2f4ce authored by Neil Armstrong's avatar Neil Armstrong Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8450: add dp controller 



Add the Display Port controller subnode to the MDSS node.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-5-d78313cbc41d@linaro.org
parent d3054cec

arch/arm64/boot/dts/qcom/sm8450.dtsi

+79 −0
Original line number Diff line number Diff line
@@ -2749,6 +2749,13 @@ dpu_intf2_out: endpoint { 
							remote-endpoint = <&mdss_dsi1_in>;

						};

					};



					port@2 {

						reg = <2>;

						dpu_intf0_out: endpoint {

							remote-endpoint = <&mdss_dp0_in>;

						};

					};

				};



				mdp_opp_table: opp-table {
@@ -2781,6 +2788,78 @@ opp-500000000 { 
				};

			};



			mdss_dp0: displayport-controller@ae90000 {

				compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";

				reg = <0 0xae90000 0 0x200>,

				      <0 0xae90200 0 0x200>,

				      <0 0xae90400 0 0xc00>,

				      <0 0xae91000 0 0x400>,

				      <0 0xae91400 0 0x400>;

				interrupt-parent = <&mdss>;

				interrupts = <12>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;

				clock-names = "core_iface",

					      "core_aux",

					      "ctrl_link",

					      "ctrl_link_iface",

					      "stream_pixel";



				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;

				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;



				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

				phy-names = "dp";



				#sound-dai-cells = <0>;



				operating-points-v2 = <&dp_opp_table>;

				power-domains = <&rpmhpd SM8450_MMCX>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdss_dp0_in: endpoint {

							remote-endpoint = <&dpu_intf0_out>;

						};

					};

				};



				dp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-160000000 {

						opp-hz = /bits/ 64 <160000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-270000000 {

						opp-hz = /bits/ 64 <270000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-540000000 {

						opp-hz = /bits/ 64 <540000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-810000000 {

						opp-hz = /bits/ 64 <810000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			mdss_dsi0: dsi@ae94000 {

				compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae94000 0 0x400>;