Commit bf3ee3db authored by Mrinmay Sarkar's avatar Mrinmay Sarkar Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sa8775p-ride: enable pcie nodes 



Enable pcie0, pcie1 nodes and their respective phy's.

Signed-off-by: default avatarMrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689960276-29266-5-git-send-email-quic_msarkar@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 489f14be

arch/arm64/boot/dts/qcom/sa8775p-ride.dts

+80 −0
Original line number Diff line number Diff line
@@ -552,6 +552,86 @@ qup_uart17_rx: qup0-uart17-rx-pins { 
			bias-pull-down;

		};

	};



	pcie0_default_state: pcie0-default-state {

		perst-pins {

			pins = "gpio2";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-down;

		};



		clkreq-pins {

			pins = "gpio1";

			function = "pcie0_clkreq";

			drive-strength = <2>;

			bias-pull-up;

		};



		wake-pins {

			pins = "gpio0";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie1_default_state: pcie1-default-state {

		perst-pins {

			pins = "gpio4";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-down;

		};



		clkreq-pins {

			pins = "gpio3";

			function = "pcie1_clkreq";

			drive-strength = <2>;

			bias-pull-up;

		};



		wake-pins {

			pins = "gpio5";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

		};

	};

};



&pcie0 {

	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;



	pinctrl-names = "default";

	pinctrl-0 = <&pcie0_default_state>;



	status = "okay";

};



&pcie1 {

	perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;



	pinctrl-names = "default";

	pinctrl-0 = <&pcie1_default_state>;



	status = "okay";

};



&pcie0_phy {

	vdda-phy-supply = <&vreg_l5a>;

	vdda-pll-supply = <&vreg_l1c>;



	status = "okay";

};



&pcie1_phy {

	vdda-phy-supply = <&vreg_l5a>;

	vdda-pll-supply = <&vreg_l1c>;



	status = "okay";

};



&uart10 {