Commit c0ea81b4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'usb-4.21-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 

Pull USB/PHY updates from Greg KH:
 "Here is the big set of USB and PHY driver patches for 4.21-rc1.

  All of the usual bits are in here:

  - loads of USB gadget driver updates and additions

  - new device ids

  - phy driver updates

  - xhci reworks and new features

  - typec updates

  Full details are in the shortlog.

  All of these have been in linux-next for a long time with no reported
  issues"

* tag 'usb-4.21-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (142 commits)
  USB: serial: option: add Fibocom NL678 series
  cdc-acm: fix abnormal DATA RX issue for Mediatek Preloader.
  usb: r8a66597: Fix a possible concurrency use-after-free bug in r8a66597_endpoint_disable()
  usb: typec: tcpm: Extend the matching rules on PPS APDO selection
  usb: typec: Improve Alt Mode documentation
  usb: musb: dsps: fix runtime pm for peripheral mode
  usb: musb: dsps: fix otg state machine
  USB: serial: pl2303: add ids for Hewlett-Packard HP POS pole displays
  usb: renesas_usbhs: add support for RZ/G2E
  usb: ehci-omap: Fix deferred probe for phy handling
  usb: roles: Add a description for the class to Kconfig
  usb: renesas_usbhs: mark PM functions as __maybe_unused
  usb: core: Remove unnecessary memset()
  usb: host: isp1362-hcd: convert to DEFINE_SHOW_ATTRIBUTE
  phy: qcom-qmp: Expose provided clocks to DT
  dt-bindings: phy-qcom-qmp: Move #clock-cells to child
  phy: qcom-qmp: Utilize fully-specified DT registers
  dt-bindings: phy-qcom-qmp: Fix register underspecification
  phy: ti: fix semicolon.cocci warnings
  phy: dphy: Add configuration helpers
  ...
parents 4d6ad6fb 4b2c01ad

Documentation/devicetree/bindings/connector/usb-connector.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -14,6 +14,8 @@ Optional properties: 
- label: symbolic name for the connector,

- label: symbolic name for the connector,

- type: size of the connector, should be specified in case of USB-A, USB-B

- type: size of the connector, should be specified in case of USB-A, USB-B

  non-fullsize connectors: "mini", "micro".

  non-fullsize connectors: "mini", "micro".

- self-powered: Set this property if the usb device that has its own power

  source.





Optional properties for usb-c-connector:

Optional properties for usb-c-connector:

- power-role: should be one of "source", "sink" or "dual"(DRP) if typec

- power-role: should be one of "source", "sink" or "dual"(DRP) if typec

Documentation/devicetree/bindings/net/cpsw.txt

+7 −1
Original line number Original line Diff line number Diff line
@@ -22,7 +22,8 @@ Required properties: 
- cpsw-phy-sel		: Specifies the phandle to the CPSW phy mode selection

- cpsw-phy-sel		: Specifies the phandle to the CPSW phy mode selection

			  device. See also cpsw-phy-sel.txt for it's binding.

			  device. See also cpsw-phy-sel.txt for it's binding.

			  Note that in legacy cases cpsw-phy-sel may be

			  Note that in legacy cases cpsw-phy-sel may be

			  a child device instead of a phandle.

			  a child device instead of a phandle

			  (DEPRECATED, use phys property instead).





Optional properties:

Optional properties:

- ti,hwmods		: Must be "cpgmac0"

- ti,hwmods		: Must be "cpgmac0"
@@ -44,6 +45,7 @@ Optional properties: 
Slave Properties:

Slave Properties:

Required properties:

Required properties:

- phy-mode		: See ethernet.txt file in the same directory

- phy-mode		: See ethernet.txt file in the same directory

- phys			: phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)





Optional properties:

Optional properties:

- dual_emac_res_vlan	: Specifies VID to be used to segregate the ports

- dual_emac_res_vlan	: Specifies VID to be used to segregate the ports
@@ -85,12 +87,14 @@ Examples: 
			phy-mode = "rgmii-txid";

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 1 0>;

		};

		};

		cpsw_emac1: slave@1 {

		cpsw_emac1: slave@1 {

			phy_id = <&davinci_mdio>, <1>;

			phy_id = <&davinci_mdio>, <1>;

			phy-mode = "rgmii-txid";

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 2 0>;

		};

		};

	};

	};
@@ -114,11 +118,13 @@ Examples: 
			phy-mode = "rgmii-txid";

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 1 0>;

		};

		};

		cpsw_emac1: slave@1 {

		cpsw_emac1: slave@1 {

			phy_id = <&davinci_mdio>, <1>;

			phy_id = <&davinci_mdio>, <1>;

			phy-mode = "rgmii-txid";

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 2 0>;

		};

		};

	};
 
	};

Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt

0 → 100644
+17 −0
Original line number Original line Diff line number Diff line 
* Freescale i.MX8MQ USB3 PHY binding



Required properties:

- compatible:	Should be "fsl,imx8mq-usb-phy"

- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

- reg:		The base address and length of the registers

- clocks:	phandles to the clocks for each clock listed in clock-names

- clock-names:	must contain "phy"



Example:

	usb3_phy0: phy@381f0040 {

		compatible = "fsl,imx8mq-usb-phy";

		reg = <0x381f0040 0x40>;

		clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;

		clock-names = "phy";

		#phy-cells = <0>;

	};

Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

+65 −12
Original line number Original line Diff line number Diff line
@@ -25,10 +25,6 @@ Required properties: 
  - For all others:

  - For all others:

    - The reg-names property shouldn't be defined.

    - The reg-names property shouldn't be defined.





 - #clock-cells: must be 1

    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe

      interface (for pipe based PHYs). These clock are then gate-controlled

      by gcc.

 - #address-cells: must be 1

 - #address-cells: must be 1

 - #size-cells: must be 1

 - #size-cells: must be 1

 - ranges: must be present

 - ranges: must be present
@@ -82,27 +78,33 @@ Required nodes: 
 - Each device node of QMP phy is required to have as many child nodes as

 - Each device node of QMP phy is required to have as many child nodes as

   the number of lanes the PHY has.

   the number of lanes the PHY has.





Required properties for child node:

Required properties for child nodes of PCIe PHYs (one child per lane):

 - reg: list of offset and length pairs of register sets for PHY blocks -

 - reg: list of offset and length pairs of register sets for PHY blocks -

	- index 0: tx

	tx, rx, pcs, and pcs_misc (optional).

	- index 1: rx

 - #phy-cells: must be 0

	- index 2: pcs

	- index 3: pcs_misc (optional)





Required properties for a single "lanes" child node of non-PCIe PHYs:

 - reg: list of offset and length pairs of register sets for PHY blocks

	For 1-lane devices:

		tx, rx, pcs, and (optionally) pcs_misc

	For 2-lane devices:

		tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc

 - #phy-cells: must be 0

 - #phy-cells: must be 0





Required properties child node of pcie and usb3 qmp phys:

Required properties for child node of PCIe and USB3 qmp phys:

 - clocks: a list of phandles and clock-specifier pairs,

 - clocks: a list of phandles and clock-specifier pairs,

	   one for each entry in clock-names.

	   one for each entry in clock-names.

 - clock-names: Must contain following:

 - clock-names: Must contain following:

		 "pipe<lane-number>" for pipe clock specific to each lane.

		 "pipe<lane-number>" for pipe clock specific to each lane.

 - clock-output-names: Name of the PHY clock that will be the parent for

 - clock-output-names: Name of the PHY clock that will be the parent for

		       the above pipe clock.

		       the above pipe clock.



	For "qcom,ipq8074-qmp-pcie-phy":

	For "qcom,ipq8074-qmp-pcie-phy":

		- "pcie20_phy0_pipe_clk"	Pipe Clock parent

		- "pcie20_phy0_pipe_clk"	Pipe Clock parent

			(or)

			(or)

		  "pcie20_phy1_pipe_clk"

		  "pcie20_phy1_pipe_clk"

 - #clock-cells: must be 0

    - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then

      gate-controlled by the gcc.





Required properties for child node of PHYs with lane reset, AKA:

Required properties for child node of PHYs with lane reset, AKA:

	"qcom,msm8996-qmp-pcie-phy"

	"qcom,msm8996-qmp-pcie-phy"
@@ -115,7 +117,6 @@ Example: 
	phy@34000 {

	phy@34000 {

		compatible = "qcom,msm8996-qmp-pcie-phy";

		compatible = "qcom,msm8996-qmp-pcie-phy";

		reg = <0x34000 0x488>;

		reg = <0x34000 0x488>;

		#clock-cells = <1>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		#size-cells = <1>;

		ranges;

		ranges;
@@ -137,6 +138,7 @@ Example: 
			reg = <0x35000 0x130>,

			reg = <0x35000 0x130>,

				<0x35200 0x200>,

				<0x35200 0x200>,

				<0x35400 0x1dc>;

				<0x35400 0x1dc>;

			#clock-cells = <0>;

			#phy-cells = <0>;

			#phy-cells = <0>;





			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
@@ -150,3 +152,54 @@ Example: 
		...

		...

		...

		...

	};

	};



	phy@88eb000 {

		compatible = "qcom,sdm845-qmp-usb3-uni-phy";

		reg = <0x88eb000 0x18c>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,

			 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			 <&gcc GCC_USB3_SEC_CLKREF_CLK>,

			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;

		clock-names = "aux", "cfg_ahb", "ref", "com_aux";



		resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,

			 <&gcc GCC_USB3_PHY_SEC_BCR>;

		reset-names = "phy", "common";



		lane@88eb200 {

			reg = <0x88eb200 0x128>,

			      <0x88eb400 0x1fc>,

			      <0x88eb800 0x218>,

			      <0x88eb600 0x70>;

			#clock-cells = <0>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;

			clock-names = "pipe0";

			clock-output-names = "usb3_uni_phy_pipe_clk_src";

		};

	};



	phy@1d87000 {

		compatible = "qcom,sdm845-qmp-ufs-phy";

		reg = <0x1d87000 0x18c>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		clock-names = "ref",

			      "ref_aux";

		clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		lanes@1d87400 {

			reg = <0x1d87400 0x108>,

			      <0x1d87600 0x1e0>,

			      <0x1d87c00 0x1dc>,

			      <0x1d87800 0x108>,

			      <0x1d87a00 0x1e0>;

			#phy-cells = <0>;

		};

	};

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt

+5 −3
Original line number Original line Diff line number Diff line
@@ -14,13 +14,14 @@ Required properties: 
  * allwinner,sun8i-r40-usb-phy

  * allwinner,sun8i-r40-usb-phy

  * allwinner,sun8i-v3s-usb-phy

  * allwinner,sun8i-v3s-usb-phy

  * allwinner,sun50i-a64-usb-phy

  * allwinner,sun50i-a64-usb-phy

  * allwinner,sun50i-h6-usb-phy

- reg : a list of offset + length pairs

- reg : a list of offset + length pairs

- reg-names :

- reg-names :

  * "phy_ctrl"

  * "phy_ctrl"

  * "pmu0" for H3, V3s and A64

  * "pmu0" for H3, V3s, A64 or H6

  * "pmu1"

  * "pmu1"

  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "pmu3" for sun8i-h3

  * "pmu3" for sun8i-h3 or sun50i-h6

- #phy-cells : from the generic phy bindings, must be 1

- #phy-cells : from the generic phy bindings, must be 1

- clocks : phandle + clock specifier for the phy clocks

- clocks : phandle + clock specifier for the phy clocks

- clock-names :

- clock-names :
@@ -29,12 +30,13 @@ Required properties: 
  * "usb0_phy", "usb1_phy" for sun8i

  * "usb0_phy", "usb1_phy" for sun8i

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3

  * "usb0_phy" and "usb3_phy" for sun50i-h6

- resets : a list of phandle + reset specifier pairs

- resets : a list of phandle + reset specifier pairs

- reset-names :

- reset-names :

  * "usb0_reset"

  * "usb0_reset"

  * "usb1_reset"

  * "usb1_reset"

  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "usb3_reset" for sun8i-h3

  * "usb3_reset" for sun8i-h3 and sun50i-h6





Optional properties:

Optional properties:

- usb0_id_det-gpios : gpio phandle for reading the otg id pin value

- usb0_id_det-gpios : gpio phandle for reading the otg id pin value