Commit c186c13e authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Drop unnecessary DCN guards 



[Why & How]
DC is littered with many DCN guards that are not needed.
Drop them.

Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bf77fda0

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

+0 −2
Original line number Diff line number Diff line
@@ -47,9 +47,7 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c 
		 */

		memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));

		dc->vm_pa_config.valid = true;

#if defined(CONFIG_DRM_AMD_DC_DCN)

		dc_z10_save_init(dc);

#endif

	}



	return num_vmids;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+0 −2
Original line number Diff line number Diff line
@@ -421,7 +421,6 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi 
	}

}



#ifdef CONFIG_DRM_AMD_DC_DCN

/**

 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command

 *
@@ -776,7 +775,6 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 
	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);

	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);

}

#endif



bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)

{

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+15 −12
Original line number Diff line number Diff line
@@ -930,7 +930,13 @@ static bool dce112_program_pix_clk( 
		REG_WRITE(MODULO[inst], dp_dto_ref_100hz);



		/* Enable DTO */

		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

					DP_DTO0_ENABLE, 1,

					PIPE0_DTO_SRC_SEL, 1);

		else

			REG_UPDATE(PIXEL_RATE_CNTL[inst],

					DP_DTO0_ENABLE, 1);

		return true;

	}

	/* First disable SS
@@ -995,7 +1001,6 @@ static bool dcn31_program_pix_clk( 
			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);

		}

#if defined(CONFIG_DRM_AMD_DC_DCN)

		/* Enable DTO */

		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

			if (encoding == DP_128b_132b_ENCODING)
@@ -1009,9 +1014,6 @@ static bool dcn31_program_pix_clk( 
		else

			REG_UPDATE(PIXEL_RATE_CNTL[inst],

					DP_DTO0_ENABLE, 1);

#else

		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

#endif

	} else {

		if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {

			unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
@@ -1023,7 +1025,6 @@ static bool dcn31_program_pix_clk( 
			REG_WRITE(MODULO[inst], dp_dto_ref_100hz);



			/* Enable DTO */

	#if defined(CONFIG_DRM_AMD_DC_DCN)

			if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

						DP_DTO0_ENABLE, 1,
@@ -1031,17 +1032,12 @@ static bool dcn31_program_pix_clk( 
			else

				REG_UPDATE(PIXEL_RATE_CNTL[inst],

						DP_DTO0_ENABLE, 1);

	#else

			REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

	#endif

			return true;

		}



#if defined(CONFIG_DRM_AMD_DC_DCN)

		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

			REG_UPDATE(PIXEL_RATE_CNTL[inst],

					PIPE0_DTO_SRC_SEL, 0);

#endif



		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/

		bp_pc_params.controller_id = pix_clk_params->controller_id;
@@ -1274,7 +1270,14 @@ static bool dcn3_program_pix_clk( 
			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);

		}

		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

		/* Enable DTO */

		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

					DP_DTO0_ENABLE, 1,

					PIPE0_DTO_SRC_SEL, 1);

		else

			REG_UPDATE(PIXEL_RATE_CNTL[inst],

					DP_DTO0_ENABLE, 1);

	} else

		// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table

		dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

+0 −6
Original line number Diff line number Diff line
@@ -204,23 +204,17 @@ 
	type DP_DTO0_MODULO; \

	type DP_DTO0_ENABLE;



#if defined(CONFIG_DRM_AMD_DC_DCN)

#define CS_REG_FIELD_LIST_DCN32(type) \

	type PIPE0_DTO_SRC_SEL;

#endif



struct dce110_clk_src_shift {

	CS_REG_FIELD_LIST(uint8_t)

#if defined(CONFIG_DRM_AMD_DC_DCN)

	CS_REG_FIELD_LIST_DCN32(uint8_t)

#endif

};



struct dce110_clk_src_mask{

	CS_REG_FIELD_LIST(uint32_t)

#if defined(CONFIG_DRM_AMD_DC_DCN)

	CS_REG_FIELD_LIST_DCN32(uint32_t)

#endif

};



struct dce110_clk_src_regs {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

+0 −5
Original line number Diff line number Diff line
@@ -23,8 +23,6 @@ 
 *

 */



#if defined(CONFIG_DRM_AMD_DC_DCN)



#include "reg_helper.h"

#include "resource.h"

#include "dwb.h"
@@ -129,6 +127,3 @@ void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, 
	dwbc10->dwbc_shift = dwbc_shift;

	dwbc10->dwbc_mask = dwbc_mask;

}
 




#endif