Commit c1dd5d29 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.0-2022-08-31' of... 

Merge tag 'amd-drm-fixes-6.0-2022-08-31' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.0-2022-08-31:

amdgpu:
- FRU error message fix
- MES 11 updates
- DCN 3.2.x fixes
- DCN 3.1.4 fixes
- Fix possible use after free in CS IOCTL
- SMU 13.0.x fixes
- Fix iolink reporting on devices with direct connections to CPU
- GFX10 tap delay firmware fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220831212312.5921-1-alexander.deucher@amd.com
parents a71f3950 39c84b8e

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −1
Original line number Diff line number Diff line
@@ -5524,7 +5524,8 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 
		~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);

	resource_size_t aper_limit =

		adev->gmc.aper_base + adev->gmc.aper_size - 1;

	bool p2p_access = !(pci_p2pdma_distance_many(adev->pdev,

	bool p2p_access = !adev->gmc.xgmi.connected_to_cpu &&

			  !(pci_p2pdma_distance_many(adev->pdev,

					&peer_adev->dev, 1, true) < 0);



	return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&

drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c

+7 −2
Original line number Diff line number Diff line
@@ -66,10 +66,15 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev) 
		return true;

	case CHIP_SIENNA_CICHLID:

		if (strnstr(atom_ctx->vbios_version, "D603",

		    sizeof(atom_ctx->vbios_version))) {

			if (strnstr(atom_ctx->vbios_version, "D603GLXE",

			    sizeof(atom_ctx->vbios_version)))

			return true;

				return false;

			else

				return true;

		} else {

			return false;

		}

	default:

		return false;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+4 −1
Original line number Diff line number Diff line
@@ -159,6 +159,9 @@ void amdgpu_job_free(struct amdgpu_job *job) 
	amdgpu_sync_free(&job->sync);

	amdgpu_sync_free(&job->sched_sync);



	if (!job->hw_fence.ops)

		kfree(job);

	else

		dma_fence_put(&job->hw_fence);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+1 −1
Original line number Diff line number Diff line
@@ -2401,7 +2401,7 @@ static int psp_load_smu_fw(struct psp_context *psp) 
static bool fw_load_skip_check(struct psp_context *psp,

			       struct amdgpu_firmware_info *ucode)

{

	if (!ucode->fw)

	if (!ucode->fw || !ucode->ucode_size)

		return true;



	if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+35 −25
Original line number Diff line number Diff line
@@ -4274,35 +4274,45 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 


		}



		if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];

		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;