Loading drivers/video/via/hw.c +1 −0 Original line number Diff line number Diff line Loading @@ -62,6 +62,7 @@ static struct pll_map pll_value[] = { CX700_52_977M, VX855_52_977M}, {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M, VX855_56_250M}, {CLK_57_275M, 0, 0, 0, VX855_57_275M}, {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M, VX855_60_466M}, {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, Loading drivers/video/via/ioctl.h +1 −1 Original line number Diff line number Diff line Loading @@ -75,7 +75,7 @@ /*SAMM operation flag*/ #define OP_SAMM 0x80 #define LCD_PANEL_ID_MAXIMUM 22 #define LCD_PANEL_ID_MAXIMUM 23 #define STATE_ON 0x1 #define STATE_OFF 0x0 Loading drivers/video/via/lcd.c +9 −0 Original line number Diff line number Diff line Loading @@ -398,6 +398,15 @@ static void fp_id_to_vindex(int panel_id) viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; viaparinfo->lvds_setting_info->LCDDithering = 1; break; case 0x17: /* OLPC XO-1.5 panel */ viaparinfo->lvds_setting_info->lcd_panel_hres = 1200; viaparinfo->lvds_setting_info->lcd_panel_vres = 900; viaparinfo->lvds_setting_info->lcd_panel_id = LCD_PANEL_IDD_1200X900; viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; viaparinfo->lvds_setting_info->LCDDithering = 0; break; default: viaparinfo->lvds_setting_info->lcd_panel_hres = 800; viaparinfo->lvds_setting_info->lcd_panel_vres = 600; Loading drivers/video/via/lcd.h +2 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,8 @@ #define LCD_PANEL_IDB_1360X768 0x0B /* Resolution: 480x640, Channel: single, Dithering: Enable */ #define LCD_PANEL_IDC_480X640 0x0C /* Resolution: 1200x900, Channel: single, Dithering: Disable */ #define LCD_PANEL_IDD_1200X900 0x0D extern int viafb_LCD2_ON; Loading drivers/video/via/share.h +7 −0 Original line number Diff line number Diff line Loading @@ -570,6 +570,10 @@ #define M1200X720_R60_HSP NEGATIVE #define M1200X720_R60_VSP POSITIVE /* 1200x900@60 Sync Polarity (DCON) */ #define M1200X900_R60_HSP NEGATIVE #define M1200X900_R60_VSP NEGATIVE /* 1280x600@60 Sync Polarity (GTF Mode) */ #define M1280x600_R60_HSP NEGATIVE #define M1280x600_R60_VSP POSITIVE Loading Loading @@ -651,6 +655,7 @@ #define CLK_52_406M 52406000 #define CLK_52_977M 52977000 #define CLK_56_250M 56250000 #define CLK_57_275M 57275000 #define CLK_60_466M 60466000 #define CLK_61_500M 61500000 #define CLK_65_000M 65000000 Loading Loading @@ -939,6 +944,7 @@ #define VX855_52_406M 0x00580C03 #define VX855_52_977M 0x00940C05 #define VX855_56_250M 0x009D0C05 #define VX855_57_275M 0x009D8C85 /* Used by XO panel */ #define VX855_60_466M 0x00A90C05 #define VX855_61_500M 0x00AC0C05 #define VX855_65_000M 0x006D0C03 Loading Loading @@ -1065,6 +1071,7 @@ #define RES_1600X1200_60HZ_PIXCLOCK 6172 #define RES_1600X1200_75HZ_PIXCLOCK 4938 #define RES_1280X720_60HZ_PIXCLOCK 13426 #define RES_1200X900_60HZ_PIXCLOCK 17459 #define RES_1920X1080_60HZ_PIXCLOCK 5787 #define RES_1400X1050_60HZ_PIXCLOCK 8214 #define RES_1400X1050_75HZ_PIXCLOCK 6410 Loading Loading
drivers/video/via/hw.c +1 −0 Original line number Diff line number Diff line Loading @@ -62,6 +62,7 @@ static struct pll_map pll_value[] = { CX700_52_977M, VX855_52_977M}, {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M, VX855_56_250M}, {CLK_57_275M, 0, 0, 0, VX855_57_275M}, {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M, VX855_60_466M}, {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, Loading
drivers/video/via/ioctl.h +1 −1 Original line number Diff line number Diff line Loading @@ -75,7 +75,7 @@ /*SAMM operation flag*/ #define OP_SAMM 0x80 #define LCD_PANEL_ID_MAXIMUM 22 #define LCD_PANEL_ID_MAXIMUM 23 #define STATE_ON 0x1 #define STATE_OFF 0x0 Loading
drivers/video/via/lcd.c +9 −0 Original line number Diff line number Diff line Loading @@ -398,6 +398,15 @@ static void fp_id_to_vindex(int panel_id) viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; viaparinfo->lvds_setting_info->LCDDithering = 1; break; case 0x17: /* OLPC XO-1.5 panel */ viaparinfo->lvds_setting_info->lcd_panel_hres = 1200; viaparinfo->lvds_setting_info->lcd_panel_vres = 900; viaparinfo->lvds_setting_info->lcd_panel_id = LCD_PANEL_IDD_1200X900; viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; viaparinfo->lvds_setting_info->LCDDithering = 0; break; default: viaparinfo->lvds_setting_info->lcd_panel_hres = 800; viaparinfo->lvds_setting_info->lcd_panel_vres = 600; Loading
drivers/video/via/lcd.h +2 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,8 @@ #define LCD_PANEL_IDB_1360X768 0x0B /* Resolution: 480x640, Channel: single, Dithering: Enable */ #define LCD_PANEL_IDC_480X640 0x0C /* Resolution: 1200x900, Channel: single, Dithering: Disable */ #define LCD_PANEL_IDD_1200X900 0x0D extern int viafb_LCD2_ON; Loading
drivers/video/via/share.h +7 −0 Original line number Diff line number Diff line Loading @@ -570,6 +570,10 @@ #define M1200X720_R60_HSP NEGATIVE #define M1200X720_R60_VSP POSITIVE /* 1200x900@60 Sync Polarity (DCON) */ #define M1200X900_R60_HSP NEGATIVE #define M1200X900_R60_VSP NEGATIVE /* 1280x600@60 Sync Polarity (GTF Mode) */ #define M1280x600_R60_HSP NEGATIVE #define M1280x600_R60_VSP POSITIVE Loading Loading @@ -651,6 +655,7 @@ #define CLK_52_406M 52406000 #define CLK_52_977M 52977000 #define CLK_56_250M 56250000 #define CLK_57_275M 57275000 #define CLK_60_466M 60466000 #define CLK_61_500M 61500000 #define CLK_65_000M 65000000 Loading Loading @@ -939,6 +944,7 @@ #define VX855_52_406M 0x00580C03 #define VX855_52_977M 0x00940C05 #define VX855_56_250M 0x009D0C05 #define VX855_57_275M 0x009D8C85 /* Used by XO panel */ #define VX855_60_466M 0x00A90C05 #define VX855_61_500M 0x00AC0C05 #define VX855_65_000M 0x006D0C03 Loading Loading @@ -1065,6 +1071,7 @@ #define RES_1600X1200_60HZ_PIXCLOCK 6172 #define RES_1600X1200_75HZ_PIXCLOCK 4938 #define RES_1280X720_60HZ_PIXCLOCK 13426 #define RES_1200X900_60HZ_PIXCLOCK 17459 #define RES_1920X1080_60HZ_PIXCLOCK 5787 #define RES_1400X1050_60HZ_PIXCLOCK 8214 #define RES_1400X1050_75HZ_PIXCLOCK 6410 Loading