Commit c2258a94 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Neil Armstrong
Browse files

arm64: dts: amlogic: add missing cache properties 



As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent cb3f4e8c

arch/arm64/boot/dts/amlogic/meson-a1.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ cpu1: cpu@1 { 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ cpu3: cpu@3 { 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ cpu3: cpu@3 { 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/amlogic/meson-g12b.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ cpu103: cpu@103 { 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

};

arch/arm64/boot/dts/amlogic/meson-gx.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ cpu3: cpu@3 { 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};