Commit c31112fb authored by Rob Clark's avatar Rob Clark Committed by Will Deacon
Browse files

iommu/arm-smmu-qcom: Fix TTBR0 read 



It is a 64b register, lets not lose the upper bits.

Fixes: ab5df7b9 ("iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info")
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211108171724.470973-1-robdclark@gmail.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent ae377d34

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static void qcom_adreno_smmu_get_fault_info(const void *cookie, 
	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);

	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);

	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));

	info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);

	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);

	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);

}