Commit c3833a22 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
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media: ccs-pll: Don't use div_u64 to divide a 32-bit number 



pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to
divide it.

Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 58379119

drivers/media/i2c/ccs-pll.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -445,7 +445,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, 
		min_pre_pll_clk_div, max_pre_pll_clk_div);

		min_pre_pll_clk_div, max_pre_pll_clk_div);





	i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);

	i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);

	mul = div_u64(pll->pll_op_clk_freq_hz, i);

	mul = pll->pll_op_clk_freq_hz / i;

	div = pll->ext_clk_freq_hz / i;

	div = pll->ext_clk_freq_hz / i;

	dev_dbg(dev, "mul %u / div %u\n", mul, div);

	dev_dbg(dev, "mul %u / div %u\n", mul, div);