drm/i915/hwmon: Show device level energy usage (c41b8bdc) · Commits · jan.koester / Linux

Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -25,3 +25,11 @@ Contact: intel-gfx@lists.freedesktop.org
	Description: RO. Card default power limit (default TDP setting).		Description: RO. Card default power limit (default TDP setting).

	Only supported for particular Intel i915 graphics platforms.		Only supported for particular Intel i915 graphics platforms.

			What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
			Date: February 2023
			KernelVersion: 6.2
			Contact: intel-gfx@lists.freedesktop.org
			Description: RO. Energy input of device in microjoules.

			Only supported for particular Intel i915 graphics platforms.

drivers/gpu/drm/i915/i915_hwmon.c

+104 −2

Original line number	Original line	Diff line number	Diff line
	@@ -17,21 +17,30 @@
	* SF_* - scale factors for particular quantities according to hwmon spec.		* SF_* - scale factors for particular quantities according to hwmon spec.
	* - voltage - millivolts		* - voltage - millivolts
	* - power - microwatts		* - power - microwatts
			* - energy - microjoules
	*/		*/
	#define SF_VOLTAGE 1000		#define SF_VOLTAGE 1000
	#define SF_POWER 1000000		#define SF_POWER 1000000
			#define SF_ENERGY 1000000

	struct hwm_reg {		struct hwm_reg {
	i915_reg_t gt_perf_status;		i915_reg_t gt_perf_status;
	i915_reg_t pkg_power_sku_unit;		i915_reg_t pkg_power_sku_unit;
	i915_reg_t pkg_power_sku;		i915_reg_t pkg_power_sku;
	i915_reg_t pkg_rapl_limit;		i915_reg_t pkg_rapl_limit;
			i915_reg_t energy_status_all;
			};

			struct hwm_energy_info {
			u32 reg_val_prev;
			long accum_energy; /* Accumulated energy for energy1_input */
	};		};

	struct hwm_drvdata {		struct hwm_drvdata {
	struct i915_hwmon *hwmon;		struct i915_hwmon *hwmon;
	struct intel_uncore *uncore;		struct intel_uncore *uncore;
	struct device *hwmon_dev;		struct device *hwmon_dev;
			struct hwm_energy_info ei; /* Energy info for energy1_input */
	char name[12];		char name[12];
	};		};

	@@ -40,6 +49,7 @@ struct i915_hwmon {
	struct mutex hwmon_lock; /* counter overflow logic and rmw */		struct mutex hwmon_lock; /* counter overflow logic and rmw */
	struct hwm_reg rg;		struct hwm_reg rg;
	int scl_shift_power;		int scl_shift_power;
			int scl_shift_energy;
	};		};

	static void		static void
	@@ -98,9 +108,58 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
	bits_to_clear, bits_to_set);		bits_to_clear, bits_to_set);
	}		}

			/*
			* hwm_energy - Obtain energy value
			*
			* The underlying energy hardware register is 32-bits and is subject to
			* overflow. How long before overflow? For example, with an example
			* scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
			* a power draw of 1000 watts, the 32-bit counter will overflow in
			* approximately 4.36 minutes.
			*
			* Examples:
			* 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
			* 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
			*
			* The function significantly increases overflow duration (from 4.36
			* minutes) by accumulating the energy register into a 'long' as allowed by
			* the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
			* a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
			* hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
			* energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
			*/
			static void
			hwm_energy(struct hwm_drvdata ddat, long energy)
			{
			struct intel_uncore *uncore = ddat->uncore;
			struct i915_hwmon *hwmon = ddat->hwmon;
			struct hwm_energy_info *ei = &ddat->ei;
			intel_wakeref_t wakeref;
			i915_reg_t rgaddr;
			u32 reg_val;

			rgaddr = hwmon->rg.energy_status_all;

			mutex_lock(&hwmon->hwmon_lock);

			with_intel_runtime_pm(uncore->rpm, wakeref)
			reg_val = intel_uncore_read(uncore, rgaddr);

			if (reg_val >= ei->reg_val_prev)
			ei->accum_energy += reg_val - ei->reg_val_prev;
			else
			ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
			ei->reg_val_prev = reg_val;

			*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
			hwmon->scl_shift_energy);
			mutex_unlock(&hwmon->hwmon_lock);
			}

	static const struct hwmon_channel_info *hwm_info[] = {		static const struct hwmon_channel_info *hwm_info[] = {
	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),		HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
	HWMON_CHANNEL_INFO(power, HWMON_P_MAX \| HWMON_P_RATED_MAX),		HWMON_CHANNEL_INFO(power, HWMON_P_MAX \| HWMON_P_RATED_MAX),
			HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
	NULL		NULL
	};		};

	@@ -194,6 +253,33 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
	}		}
	}		}

			static umode_t
			hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
			{
			struct i915_hwmon *hwmon = ddat->hwmon;
			i915_reg_t rgaddr;

			switch (attr) {
			case hwmon_energy_input:
			rgaddr = hwmon->rg.energy_status_all;
			return i915_mmio_reg_valid(rgaddr) ? 0444 : 0;
			default:
			return 0;
			}
			}

			static int
			hwm_energy_read(struct hwm_drvdata ddat, u32 attr, long val)
			{
			switch (attr) {
			case hwmon_energy_input:
			hwm_energy(ddat, val);
			return 0;
			default:
			return -EOPNOTSUPP;
			}
			}

	static umode_t		static umode_t
	hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,		hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
	u32 attr, int channel)		u32 attr, int channel)
	@@ -205,6 +291,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
	return hwm_in_is_visible(ddat, attr);		return hwm_in_is_visible(ddat, attr);
	case hwmon_power:		case hwmon_power:
	return hwm_power_is_visible(ddat, attr, channel);		return hwm_power_is_visible(ddat, attr, channel);
			case hwmon_energy:
			return hwm_energy_is_visible(ddat, attr);
	default:		default:
	return 0;		return 0;
	}		}
	@@ -221,6 +309,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
	return hwm_in_read(ddat, attr, val);		return hwm_in_read(ddat, attr, val);
	case hwmon_power:		case hwmon_power:
	return hwm_power_read(ddat, attr, channel, val);		return hwm_power_read(ddat, attr, channel, val);
			case hwmon_energy:
			return hwm_energy_read(ddat, attr, val);
	default:		default:
	return -EOPNOTSUPP;		return -EOPNOTSUPP;
	}		}
	@@ -256,8 +346,10 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
	{		{
	struct i915_hwmon *hwmon = i915->hwmon;		struct i915_hwmon *hwmon = i915->hwmon;
	struct intel_uncore *uncore = &i915->uncore;		struct intel_uncore *uncore = &i915->uncore;
			struct hwm_drvdata *ddat = &hwmon->ddat;
	intel_wakeref_t wakeref;		intel_wakeref_t wakeref;
	u32 val_sku_unit = 0;		u32 val_sku_unit = 0;
			long energy;

	/* Available for all Gen12+/dGfx */		/* Available for all Gen12+/dGfx */
	hwmon->rg.gt_perf_status = GEN12_RPSTAT1;		hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
	@@ -266,10 +358,12 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
	hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;		hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
	hwmon->rg.pkg_power_sku = PCU_PACKAGE_POWER_SKU;		hwmon->rg.pkg_power_sku = PCU_PACKAGE_POWER_SKU;
	hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;		hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
			hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
	} else {		} else {
	hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;		hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
	hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;		hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
	hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;		hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
			hwmon->rg.energy_status_all = INVALID_MMIO_REG;
	}		}

	with_intel_runtime_pm(uncore->rpm, wakeref) {		with_intel_runtime_pm(uncore->rpm, wakeref) {
	@@ -280,9 +374,17 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
	if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit))		if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit))
	val_sku_unit = intel_uncore_read(uncore,		val_sku_unit = intel_uncore_read(uncore,
	hwmon->rg.pkg_power_sku_unit);		hwmon->rg.pkg_power_sku_unit);
			}

	hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);		hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
	}		hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);

			/*
			* Initialize 'struct hwm_energy_info', i.e. set fields to the
			* first value of the energy register read
			*/
			if (i915_mmio_reg_valid(hwmon->rg.energy_status_all))
			hwm_energy(ddat, &energy);
	}		}

	void i915_hwmon_register(struct drm_i915_private *i915)		void i915_hwmon_register(struct drm_i915_private *i915)

drivers/gpu/drm/i915/intel_mchbar_regs.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -197,7 +197,9 @@

	#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)		#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
	#define PKG_PWR_UNIT REG_GENMASK(3, 0)		#define PKG_PWR_UNIT REG_GENMASK(3, 0)
			#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
	#define PKG_TIME_UNIT REG_GENMASK(19, 16)		#define PKG_TIME_UNIT REG_GENMASK(19, 16)
			#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)

	#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)		#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
	#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)		#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)