Commit c4381d0e authored by Bokun Zhang's avatar Bokun Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add interface to load SRIOV cap FW 



- Add interface to load SRIOV cap FW. If the FW does not
  exist, simply skip this FW loading routine.
  This FW will only be loaded under SRIOV. Other driver
  configuration will not be affected.
  By adding this interface, it will make us easier to
  prepare SRIOV Linux guest driver for different users.

- Update sysfs interface to read cap FW version.

- Refactor PSP FW loading routine under SRIOV to use a
  unified SWITCH statement instead of using IF statement

- Remove redundant amdgpu_sriov_vf() check in FW loading
  routine

Acked-by: default avatarMonk Liu <monk.liu@amd.com>
Acked-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarBokun Zhang <Bokun.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 20c5e425

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+14 −0
Original line number Diff line number Diff line
@@ -400,6 +400,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 
		fw_info->ver = adev->psp.toc.fw_version;

		fw_info->feature = adev->psp.toc.feature_version;

		break;

	case AMDGPU_INFO_FW_CAP:

		fw_info->ver = adev->psp.cap_fw_version;

		fw_info->feature = adev->psp.cap_feature_version;

		break;

	default:

		return -EINVAL;

	}
@@ -1617,6 +1621,16 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 
	seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",

		   fw_info.feature, fw_info.ver);



	/* CAP */

	if (adev->psp.cap_fw) {

		query_fw.fw_type = AMDGPU_INFO_FW_CAP;

		ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);

		if (ret)

			return ret;

		seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",

				fw_info.feature, fw_info.ver);

	}



	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);



	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+95 −13
Original line number Diff line number Diff line
@@ -259,6 +259,32 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 
	return ret;

}



static int psp_init_sriov_microcode(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;

	int ret = 0;



	switch (adev->ip_versions[MP0_HWIP][0]) {

	case IP_VERSION(9, 0, 0):

		ret = psp_init_cap_microcode(psp, "vega10");

		break;

	case IP_VERSION(11, 0, 9):

		ret = psp_init_cap_microcode(psp, "navi12");

		break;

	case IP_VERSION(11, 0, 7):

		ret = psp_init_cap_microcode(psp, "sienna_cichlid");

		break;

	case IP_VERSION(13, 0, 2):

		ret = psp_init_ta_microcode(psp, "aldebaran");

		break;

	default:

		BUG();

		break;

	}



	return ret;

}



static int psp_sw_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -273,20 +299,14 @@ static int psp_sw_init(void *handle) 
		ret = -ENOMEM;

	}



	if (!amdgpu_sriov_vf(adev)) {

	if (amdgpu_sriov_vf(adev))

		ret = psp_init_sriov_microcode(psp);

	else

		ret = psp_init_microcode(psp);

	if (ret) {

		DRM_ERROR("Failed to load psp firmware!\n");

		return ret;

	}

	} else if (amdgpu_sriov_vf(adev) &&

		   adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {

		ret = psp_init_ta_microcode(psp, "aldebaran");

		if (ret) {

			DRM_ERROR("Failed to initialize ta microcode!\n");

			return ret;

		}

	}



	memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));

	if (psp_get_runtime_db_entry(adev,
@@ -353,6 +373,10 @@ static int psp_sw_fini(void *handle) 
		release_firmware(psp->ta_fw);

		psp->ta_fw = NULL;

	}

	if (adev->psp.cap_fw) {

		release_firmware(psp->cap_fw);

		psp->cap_fw = NULL;

	}



	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||

	    adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
@@ -491,7 +515,10 @@ psp_cmd_submit_buf(struct psp_context *psp, 
		DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",

			 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,

			 psp->cmd_buf_mem->resp.status);

		if (!timeout) {

		/* If we load CAP FW, PSP must return 0 under SRIOV

		 * also return failure in case of timeout

		 */

		if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) {

			ret = -EINVAL;

			goto exit;

		}
@@ -2051,6 +2078,9 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 
			   enum psp_gfx_fw_type *type)

{

	switch (ucode->ucode_id) {

	case AMDGPU_UCODE_ID_CAP:

		*type = GFX_FW_TYPE_CAP;

		break;

	case AMDGPU_UCODE_ID_SDMA0:

		*type = GFX_FW_TYPE_SDMA0;

		break;
@@ -3217,6 +3247,58 @@ int psp_init_ta_microcode(struct psp_context *psp, 
	return err;

}



int psp_init_cap_microcode(struct psp_context *psp,

			  const char *chip_name)

{

	struct amdgpu_device *adev = psp->adev;

	char fw_name[PSP_FW_NAME_LEN];

	const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;

	struct amdgpu_firmware_info *info = NULL;

	int err = 0;



	if (!chip_name) {

		dev_err(adev->dev, "invalid chip name for cap microcode\n");

		return -EINVAL;

	}



	if (!amdgpu_sriov_vf(adev)) {

		dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");

		return -EINVAL;

	}



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);

	err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);

	if (err) {

		dev_warn(adev->dev, "cap microcode does not exist, skip\n");

		err = 0;

		goto out;

	}



	err = amdgpu_ucode_validate(adev->psp.cap_fw);

	if (err) {

		dev_err(adev->dev, "fail to initialize cap microcode\n");

		goto out;

	}



	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];

	info->ucode_id = AMDGPU_UCODE_ID_CAP;

	info->fw = adev->psp.cap_fw;

	cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)

		adev->psp.cap_fw->data;

	adev->firmware.fw_size += ALIGN(

			le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);

	adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);

	adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);

	adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);



	return 0;



out:

	release_firmware(adev->psp.cap_fw);

	adev->psp.cap_fw = NULL;

	return err;

}



static int psp_set_clockgating_state(void *handle,

				     enum amd_clockgating_state state)

{

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+9 −0
Original line number Diff line number Diff line
@@ -306,6 +306,9 @@ struct psp_context 
	/* toc firmware */

	const struct firmware		*toc_fw;



	/* cap firmware */

	const struct firmware		*cap_fw;



	/* fence buffer */

	struct amdgpu_bo		*fence_buf_bo;

	uint64_t			fence_buf_mc_addr;
@@ -327,6 +330,10 @@ struct psp_context 
	const struct firmware		*ta_fw;

	uint32_t			ta_fw_version;



	uint32_t			cap_fw_version;

	uint32_t			cap_feature_version;

	uint32_t			cap_ucode_size;



	struct ta_context		asd_context;

	struct psp_xgmi_context		xgmi_context;

	struct psp_ras_context		ras_context;
@@ -440,6 +447,8 @@ int psp_init_sos_microcode(struct psp_context *psp, 
			   const char *chip_name);

int psp_init_ta_microcode(struct psp_context *psp,

			  const char *chip_name);

int psp_init_cap_microcode(struct psp_context *psp,

			  const char *chip_name);

int psp_get_fw_attestation_records_addr(struct psp_context *psp,

					uint64_t *output_ptr);

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+1 −0
Original line number Diff line number Diff line
@@ -378,6 +378,7 @@ enum AMDGPU_UCODE_ID { 
	AMDGPU_UCODE_ID_VCN0_RAM,

	AMDGPU_UCODE_ID_VCN1_RAM,

	AMDGPU_UCODE_ID_DMCUB,

	AMDGPU_UCODE_ID_CAP,

	AMDGPU_UCODE_ID_MAXIMUM,

};

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

+1 −0
Original line number Diff line number Diff line
@@ -258,6 +258,7 @@ enum psp_gfx_fw_type { 
	GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */

	GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */

	GFX_FW_TYPE_VCN1                            = 58,   /* VCN1                     MI      */

	GFX_FW_TYPE_CAP                             = 62,   /* CAP_FW                           */

	GFX_FW_TYPE_REG_LIST                        = 67,   /* REG_LIST                 MI      */

	GFX_FW_TYPE_MAX

};