Commit c46af562 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use a fixed N value always 



Windows/BIOS always uses fixed N values. Let's match that
behaviour.

Allows us to also get rid of that constant_n quirk stuff.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-17-ville.syrjala@linux.intel.com
parent e6f29923

drivers/gpu/drm/i915/display/intel_display.c

+18 −20
Original line number Diff line number Diff line
@@ -2721,19 +2721,11 @@ intel_reduce_m_n_ratio(u32 *num, u32 *den) 
	}

}



static void compute_m_n(unsigned int m, unsigned int n,

			u32 *ret_m, u32 *ret_n,

			bool constant_n)

static void compute_m_n(u32 *ret_m, u32 *ret_n,

			u32 m, u32 n, u32 constant_n)

{

	/*

	 * Several DP dongles in particular seem to be fussy about

	 * too large link M/N values. Give N value as 0x8000 that

	 * should be acceptable by specific devices. 0x8000 is the

	 * specified fixed N value for asynchronous clock mode,

	 * which the devices expect also in synchronous clock mode.

	 */

	if (constant_n)

		*ret_n = DP_LINK_CONSTANT_N_VALUE;

		*ret_n = constant_n;

	else

		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
@@ -2745,22 +2737,28 @@ void 
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,

		       int pixel_clock, int link_clock,

		       struct intel_link_m_n *m_n,

		       bool constant_n, bool fec_enable)

		       bool fec_enable)

{

	u32 data_clock = bits_per_pixel * pixel_clock;



	if (fec_enable)

		data_clock = intel_dp_mode_to_fec_clock(data_clock);



	/*

	 * Windows/BIOS uses fixed M/N values always. Follow suit.

	 *

	 * Also several DP dongles in particular seem to be fussy

	 * about too large link M/N values. Presumably the 20bit

	 * value used by Windows/BIOS is acceptable to everyone.

	 */

	m_n->tu = 64;

	compute_m_n(data_clock,

		    link_clock * nlanes * 8,

		    &m_n->data_m, &m_n->data_n,

		    constant_n);



	compute_m_n(pixel_clock, link_clock,

		    &m_n->link_m, &m_n->link_n,

		    constant_n);

	compute_m_n(&m_n->data_m, &m_n->data_n,

		    data_clock, link_clock * nlanes * 8,

		    0x8000000);



	compute_m_n(&m_n->link_m, &m_n->link_n,

		    pixel_clock, link_clock,

		    0x80000);

}



static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/display/intel_display.h

+1 −1
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state, 
void intel_link_compute_m_n(u16 bpp, int nlanes,

			    int pixel_clock, int link_clock,

			    struct intel_link_m_n *m_n,

			    bool constant_n, bool fec_enable);

			    bool fec_enable);

u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,

			      u32 pixel_format, u64 modifier);

enum drm_mode_status

drivers/gpu/drm/i915/display/intel_dp.c

+4 −6
Original line number Diff line number Diff line
@@ -1927,7 +1927,7 @@ static bool can_enable_drrs(struct intel_connector *connector, 
static void

intel_dp_drrs_compute_config(struct intel_connector *connector,

			     struct intel_crtc_state *pipe_config,

			     int output_bpp, bool constant_n)

			     int output_bpp)

{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);

	const struct drm_display_mode *downclock_mode =
@@ -1954,7 +1954,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, 


	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,

			       pipe_config->port_clock, &pipe_config->dp_m2_n2,

			       constant_n, pipe_config->fec_enable);

			       pipe_config->fec_enable);



	/* FIXME: abstract this better */

	if (pipe_config->splitter.enable)
@@ -2029,7 +2029,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	const struct drm_display_mode *fixed_mode;

	struct intel_connector *connector = intel_dp->attached_connector;

	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);

	int ret = 0, output_bpp;



	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
@@ -2108,7 +2107,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
			       adjusted_mode->crtc_clock,

			       pipe_config->port_clock,

			       &pipe_config->dp_m_n,

			       constant_n, pipe_config->fec_enable);

			       pipe_config->fec_enable);



	/* FIXME: abstract this better */

	if (pipe_config->splitter.enable)
@@ -2119,8 +2118,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 


	intel_vrr_compute_config(pipe_config, conn_state);

	intel_psr_compute_config(intel_dp, pipe_config, conn_state);

	intel_dp_drrs_compute_config(connector, pipe_config,

				     output_bpp, constant_n);

	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);

	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);

	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

+1 −2
Original line number Diff line number Diff line
@@ -57,7 +57,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 
	struct drm_i915_private *i915 = to_i915(connector->base.dev);

	const struct drm_display_mode *adjusted_mode =

		&crtc_state->hw.adjusted_mode;

	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);

	int bpp, slots = -EINVAL;



	crtc_state->lane_count = limits->max_lane_count;
@@ -93,7 +92,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 
			       adjusted_mode->crtc_clock,

			       crtc_state->port_clock,

			       &crtc_state->dp_m_n,

			       constant_n, crtc_state->fec_enable);

			       crtc_state->fec_enable);

	crtc_state->dp_m_n.tu = slots;



	return 0;

drivers/gpu/drm/i915/display/intel_fdi.c

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, 
	pipe_config->fdi_lanes = lane;



	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,

			       link_bw, &pipe_config->fdi_m_n, false, false);

			       link_bw, &pipe_config->fdi_m_n, false);



	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);

	if (ret == -EDEADLK)