Commit c57247f9 authored by Vidya Sagar's avatar Vidya Sagar Committed by Lorenzo Pieralisi
Browse files

PCI: tegra: Add support for PCIe endpoint mode in Tegra194 



Add support for the endpoint mode of Synopsys DesignWare core based
dual mode PCIe controllers present in Tegra194 SoC.

Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
parent 9f04d18b

drivers/pci/controller/dwc/Kconfig

+26 −3
Original line number Diff line number Diff line
@@ -248,14 +248,37 @@ config PCI_MESON 
	  implement the driver.



config PCIE_TEGRA194

	tristate "NVIDIA Tegra194 (and later) PCIe controller"

	tristate



config PCIE_TEGRA194_HOST

	tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode"

	depends on ARCH_TEGRA_194_SOC || COMPILE_TEST

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIE_DW_HOST

	select PHY_TEGRA194_P2U

	select PCIE_TEGRA194

	help

	  Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to

	  work in host mode. There are two instances of PCIe controllers in

	  Tegra194. This controller can work either as EP or RC. In order to

	  enable host-specific features PCIE_TEGRA194_HOST must be selected and

	  in order to enable device-specific features PCIE_TEGRA194_EP must be

	  selected. This uses the DesignWare core.



config PCIE_TEGRA194_EP

	tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode"

	depends on ARCH_TEGRA_194_SOC || COMPILE_TEST

	depends on PCI_ENDPOINT

	select PCIE_DW_EP

	select PHY_TEGRA194_P2U

	select PCIE_TEGRA194

	help

	  Say Y here if you want support for DesignWare core based PCIe host

	  controller found in NVIDIA Tegra194 SoC.

	  Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to

	  work in host mode. There are two instances of PCIe controllers in

	  Tegra194. This controller can work either as EP or RC. In order to

	  enable host-specific features PCIE_TEGRA194_HOST must be selected and

	  in order to enable device-specific features PCIE_TEGRA194_EP must be

	  selected. This uses the DesignWare core.



config PCIE_UNIPHIER

	bool "Socionext UniPhier PCIe controllers"

drivers/pci/controller/dwc/pcie-designware-ep.c

+4 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) 


	pci_epc_linkup(epc);

}

EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup);



void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)

{
@@ -25,6 +26,7 @@ void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) 


	pci_epc_init_notify(epc);

}

EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);



static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,

				   int flags)
@@ -536,6 +538,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) 


	return 0;

}

EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);



int dw_pcie_ep_init(struct dw_pcie_ep *ep)

{
@@ -630,3 +633,4 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) 


	return dw_pcie_ep_init_complete(ep);

}

EXPORT_SYMBOL_GPL(dw_pcie_ep_init);

drivers/pci/controller/dwc/pcie-tegra194.c

+665 −15

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