Commit c66846e0 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: update cached feature enablement status V3 



Need to update in cache feature enablement status after pp_feature
settings. Another fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu

V2: update smu_feature_update_enable_state() and relates
V3: use bitmap_or and bitmap_andnot

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarJack Gui <Jack.Gui@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f78c47f6

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+49 −52
Original line number Diff line number Diff line
@@ -95,6 +95,52 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) 
	return size;

}



static int smu_feature_update_enable_state(struct smu_context *smu,

					   uint64_t feature_mask,

					   bool enabled)

{

	struct smu_feature *feature = &smu->smu_feature;

	uint32_t feature_low = 0, feature_high = 0;

	int ret = 0;



	if (!smu->pm_enabled)

		return ret;



	feature_low = (feature_mask >> 0 ) & 0xffffffff;

	feature_high = (feature_mask >> 32) & 0xffffffff;



	if (enabled) {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,

						  feature_low);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,

						  feature_high);

		if (ret)

			return ret;

	} else {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,

						  feature_low);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,

						  feature_high);

		if (ret)

			return ret;

	}



	mutex_lock(&feature->mutex);

	if (enabled)

		bitmap_or(feature->enabled, feature->enabled,

				(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);

	else

		bitmap_andnot(feature->enabled, feature->enabled,

				(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);

	mutex_unlock(&feature->mutex);



	return ret;

}



int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)

{

	int ret = 0;
@@ -566,41 +612,7 @@ int smu_feature_init_dpm(struct smu_context *smu) 


	return ret;

}

int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)

{

	uint32_t feature_low = 0, feature_high = 0;

	int ret = 0;



	if (!smu->pm_enabled)

		return ret;



	feature_low = (feature_mask >> 0 ) & 0xffffffff;

	feature_high = (feature_mask >> 32) & 0xffffffff;



	if (enabled) {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,

						  feature_low);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,

						  feature_high);

		if (ret)

			return ret;



	} else {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,

						  feature_low);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,

						  feature_high);

		if (ret)

			return ret;



	}



	return ret;

}



int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)

{
@@ -630,8 +642,6 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask, 
{

	struct smu_feature *feature = &smu->smu_feature;

	int feature_id;

	uint64_t feature_mask = 0;

	int ret = 0;



	feature_id = smu_feature_get_index(smu, mask);

	if (feature_id < 0)
@@ -639,22 +649,9 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask, 


	WARN_ON(feature_id > feature->feature_num);



	feature_mask = 1ULL << feature_id;



	mutex_lock(&feature->mutex);

	ret = smu_feature_update_enable_state(smu, feature_mask, enable);

	if (ret)

		goto failed;



	if (enable)

		test_and_set_bit(feature_id, feature->enabled);

	else

		test_and_clear_bit(feature_id, feature->enabled);



failed:

	mutex_unlock(&feature->mutex);



	return ret;

	return smu_feature_update_enable_state(smu,

					       1ULL << feature_id,

					       enable);

}



int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+0 −1
Original line number Diff line number Diff line
@@ -827,7 +827,6 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); 
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);

int smu_set_display_count(struct smu_context *smu, uint32_t count);

bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);

int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);

const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);

const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);

size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);