Loading arch/sh/include/asm/system_32.h +2 −1 Original line number Diff line number Diff line Loading @@ -58,7 +58,8 @@ do { \ last = __last; \ } while (0) #define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text"))) #define __uses_jump_to_uncached \ noinline __attribute__ ((__section__ (".uncached.text"))) /* * Jump to uncached area. Loading arch/sh/mm/init.c +14 −13 Original line number Diff line number Diff line Loading @@ -23,7 +23,19 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); pgd_t swapper_pg_dir[PTRS_PER_PGD]; unsigned long cached_to_uncached = 0; #ifdef CONFIG_SUPERH32 /* * Handle trivial transitions between cached and uncached * segments, making use of the 1:1 mapping relationship in * 512MB lowmem. * * This is the offset of the uncached section from its cached alias. * Default value only valid in 29 bit mode, in 32bit mode will be * overridden in pmb_init. */ unsigned long cached_to_uncached = P2SEG - P1SEG; #endif #ifdef CONFIG_MMU static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) Loading Loading @@ -58,8 +70,6 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) } set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot)); if (cached_to_uncached) flush_tlb_one(get_asid(), addr); } Loading Loading @@ -165,15 +175,6 @@ void __init paging_init(void) #ifdef CONFIG_SUPERH32 /* Set up the uncached fixmap */ set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start)); #ifdef CONFIG_29BIT /* * Handle trivial transitions between cached and uncached * segments, making use of the 1:1 mapping relationship in * 512MB lowmem. */ cached_to_uncached = P2SEG - P1SEG; #endif #endif } Loading Loading
arch/sh/include/asm/system_32.h +2 −1 Original line number Diff line number Diff line Loading @@ -58,7 +58,8 @@ do { \ last = __last; \ } while (0) #define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text"))) #define __uses_jump_to_uncached \ noinline __attribute__ ((__section__ (".uncached.text"))) /* * Jump to uncached area. Loading
arch/sh/mm/init.c +14 −13 Original line number Diff line number Diff line Loading @@ -23,7 +23,19 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); pgd_t swapper_pg_dir[PTRS_PER_PGD]; unsigned long cached_to_uncached = 0; #ifdef CONFIG_SUPERH32 /* * Handle trivial transitions between cached and uncached * segments, making use of the 1:1 mapping relationship in * 512MB lowmem. * * This is the offset of the uncached section from its cached alias. * Default value only valid in 29 bit mode, in 32bit mode will be * overridden in pmb_init. */ unsigned long cached_to_uncached = P2SEG - P1SEG; #endif #ifdef CONFIG_MMU static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) Loading Loading @@ -58,8 +70,6 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) } set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot)); if (cached_to_uncached) flush_tlb_one(get_asid(), addr); } Loading Loading @@ -165,15 +175,6 @@ void __init paging_init(void) #ifdef CONFIG_SUPERH32 /* Set up the uncached fixmap */ set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start)); #ifdef CONFIG_29BIT /* * Handle trivial transitions between cached and uncached * segments, making use of the 1:1 mapping relationship in * 512MB lowmem. */ cached_to_uncached = P2SEG - P1SEG; #endif #endif } Loading