Unverified Commit c723b6b7 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.17-next-dts64' of... 

Merge tag 'v5.17-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8192
- add clocks to the devices
- add watchdog node
- add power domain controller node

mt8183:
- add pmic (mt6358) key board node
- add JPEG enconder node

mt7986:
- update memory node
- add clock controller for mt7986a version

* tag 'v5.17-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mediatek: update mt7986b memory node
  arm64: dts: mediatek: update mt7986a memory node
  arm64: dts: mediatek: add clock support for mt7986a
  arm64: dts: mediatek: Add mt8192 power domains controller
  arm64: dts: mt6358: add mt6358-keys node
  arm64: dts: mt8183: add jpeg enc node for mt8183
  arm64: dts: mt8192: Add watchdog node
  arm64: dts: mediatek: Correct system timer clock of MT8192
  arm64: dts: mediatek: Correct I2C clock of MT8192
  arm64: dts: mediatek: Correct Nor Flash clock of MT8192
  arm64: dts: mediatek: Correct SPI clock of MT8192
  arm64: dts: mediatek: Correct uart clock of MT8192

Link: https://lore.kernel.org/r/c2064dcc-acdc-c86b-5ef7-cb8e7ae3122f@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 29cefaaf 809967d7

arch/arm64/boot/dts/mediatek/mt6358.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
/*

 * Copyright (c) 2020 MediaTek Inc.

 */

#include <dt-bindings/input/input.h>



&pwrap {

	pmic: mt6358 {
@@ -357,5 +358,16 @@ mt6358_vsim2_reg: ldo_vsim2 { 
		mt6358rtc: mt6358rtc {

			compatible = "mediatek,mt6358-rtc";

		};



		mt6358keys: mt6358keys {

			compatible = "mediatek,mt6358-keys";

			power {

				linux,keycodes = <KEY_POWER>;

				wakeup-source;

			};

			home {

				linux,keycodes = <KEY_HOME>;

			};

		};

	};

};

arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts

+2 −1
Original line number Diff line number Diff line
@@ -19,7 +19,8 @@ chosen { 
		stdout-path = "serial0:115200n8";

	};



	memory {

	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x40000000>;

	};

};

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

+63 −5
Original line number Diff line number Diff line
@@ -6,16 +6,18 @@ 


#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/mt7986-clk.h>



/ {

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	system_clk: dummy40m {

	clk40m: oscillator@0 {

		compatible = "fixed-clock";

		clock-frequency = <40000000>;

		#clock-cells = <0>;

		clock-output-names = "clkxtal";

	};



	cpus {
@@ -98,6 +100,18 @@ gic: interrupt-controller@c000000 { 
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		infracfg: infracfg@10001000 {

			compatible = "mediatek,mt7986-infracfg", "syscon";

			reg = <0 0x10001000 0 0x1000>;

			#clock-cells = <1>;

		};



		topckgen: topckgen@1001b000 {

			compatible = "mediatek,mt7986-topckgen", "syscon";

			reg = <0 0x1001B000 0 0x1000>;

			#clock-cells = <1>;

		};



		watchdog: watchdog@1001c000 {

			compatible = "mediatek,mt7986-wdt",

				     "mediatek,mt6589-wdt";
@@ -107,6 +121,12 @@ watchdog: watchdog@1001c000 { 
			status = "disabled";

		};



		apmixedsys: apmixedsys@1001e000 {

			compatible = "mediatek,mt7986-apmixedsys";

			reg = <0 0x1001E000 0 0x1000>;

			#clock-cells = <1>;

		};



		pio: pinctrl@1001f000 {

			compatible = "mediatek,mt7986a-pinctrl";

			reg = <0 0x1001f000 0 0x1000>,
@@ -128,11 +148,25 @@ pio: pinctrl@1001f000 { 
			#interrupt-cells = <2>;

		};



		sgmiisys0: syscon@10060000 {

			compatible = "mediatek,mt7986-sgmiisys_0",

				     "syscon";

			reg = <0 0x10060000 0 0x1000>;

			#clock-cells = <1>;

		};



		sgmiisys1: syscon@10070000 {

			compatible = "mediatek,mt7986-sgmiisys_1",

				     "syscon";

			reg = <0 0x10070000 0 0x1000>;

			#clock-cells = <1>;

		};



		trng: trng@1020f000 {

			compatible = "mediatek,mt7986-rng",

				     "mediatek,mt7623-rng";

			reg = <0 0x1020f000 0 0x100>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_TRNG_CK>;

			clock-names = "rng";

			status = "disabled";

		};
@@ -142,7 +176,13 @@ uart0: serial@11002000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11002000 0 0x400>;

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_UART0_SEL>,

				 <&infracfg CLK_INFRA_UART0_CK>;

			clock-names = "baud", "bus";

			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,

					  <&infracfg CLK_INFRA_UART0_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,

						 <&topckgen CLK_TOP_UART_SEL>;

			status = "disabled";

		};
@@ -151,7 +191,11 @@ uart1: serial@11003000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11003000 0 0x400>;

			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_UART1_SEL>,

				 <&infracfg CLK_INFRA_UART1_CK>;

			clock-names = "baud", "bus";

			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;

			status = "disabled";

		};
@@ -160,10 +204,24 @@ uart2: serial@11004000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11004000 0 0x400>;

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_UART2_SEL>,

				 <&infracfg CLK_INFRA_UART2_CK>;

			clock-names = "baud", "bus";

			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;

			status = "disabled";

		};



		ethsys: syscon@15000000 {

			 #address-cells = <1>;

			 #size-cells = <1>;

			 compatible = "mediatek,mt7986-ethsys",

				      "syscon";

			 reg = <0 0x15000000 0 0x1000>;

			 #clock-cells = <1>;

			 #reset-cells = <1>;

		};



	};



};

arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts

+2 −1
Original line number Diff line number Diff line
@@ -19,7 +19,8 @@ chosen { 
		stdout-path = "serial0:115200n8";

	};



	memory {

	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x40000000>;

	};

};

arch/arm64/boot/dts/mediatek/mt8183.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -1594,6 +1594,18 @@ larb4: larb@17010000 { 
			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;

		};



		venc_jpg: venc_jpg@17030000 {

			compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";

			reg = <0 0x17030000 0 0x1000>;

			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;

			mediatek,larb = <&larb4>;

			iommus = <&iommu M4U_PORT_JPGENC_RDMA>,

				 <&iommu M4U_PORT_JPGENC_BSDMA>;

			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;

			clocks = <&vencsys CLK_VENC_JPGENC>;

			clock-names = "jpgenc";

		};



		ipu_conn: syscon@19000000 {

			compatible = "mediatek,mt8183-ipu_conn", "syscon";

			reg = <0 0x19000000 0 0x1000>;