Commit c7ad08c6 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
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wifi: rtw89: use u32_get_bits to access C2H content of PHY capability 



The definitions of bit fields in structure will be wrong in big-endian
platform, so use u32_get_bits() to access them.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220908074140.39776-2-pkshih@realtek.com
parent 8f15a8d6

drivers/net/wireless/realtek/rtw89/fw.h

+26 −15
Original line number Diff line number Diff line
@@ -63,21 +63,32 @@ enum rtw89_mac_c2h_type { 
	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF

};



struct rtw89_c2h_phy_cap {

	u32 func:7;

	u32 ack:1;

	u32 len:4;

	u32 seq:4;

	u32 rx_nss:8;

	u32 bw:8;



	u32 tx_nss:8;

	u32 prot:8;

	u32 nic:8;

	u32 wl_func:8;



	u32 hw_type:8;

} __packed;

#define RTW89_GET_C2H_PHYCAP_FUNC(info) \

	u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))

#define RTW89_GET_C2H_PHYCAP_ACK(info) \

	u32_get_bits(*((const u32 *)(info)), BIT(7))

#define RTW89_GET_C2H_PHYCAP_LEN(info) \

	u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))

#define RTW89_GET_C2H_PHYCAP_SEQ(info) \

	u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))

#define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \

	u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))

#define RTW89_GET_C2H_PHYCAP_BW(info) \

	u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))

#define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \

	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))

#define RTW89_GET_C2H_PHYCAP_PROT(info) \

	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8))

#define RTW89_GET_C2H_PHYCAP_NIC(info) \

	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16))

#define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \

	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24))

#define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \

	u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0))

#define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \

	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8))

#define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \

	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16))



enum rtw89_fw_c2h_category {

	RTW89_C2H_CAT_TEST,

drivers/net/wireless/realtek/rtw89/mac.c

+9 −8
Original line number Diff line number Diff line
@@ -2262,23 +2262,24 @@ int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 
	struct rtw89_hal *hal = &rtwdev->hal;

	const struct rtw89_chip_info *chip = rtwdev->chip;

	struct rtw89_mac_c2h_info c2h_info = {0};

	struct rtw89_c2h_phy_cap *cap =

		(struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0];

	u8 tx_nss;

	u8 rx_nss;

	u32 ret;



	ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);

	if (ret)

		return ret;



	hal->tx_nss = cap->tx_nss ?

		      min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss;

	hal->rx_nss = cap->rx_nss ?

		      min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss;

	tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg);

	rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg);



	hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;

	hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;



	rtw89_debug(rtwdev, RTW89_DBG_FW,

		    "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n",

		    hal->tx_nss, cap->tx_nss, chip->tx_nss,

		    hal->rx_nss, cap->rx_nss, chip->rx_nss);

		    hal->tx_nss, tx_nss, chip->tx_nss,

		    hal->rx_nss, rx_nss, chip->rx_nss);



	return 0;

}