Commit c89dcce4 authored by Shawn Guo's avatar Shawn Guo
Browse files

Merge branch 'imx/clk' into imx/dt

parents 3a35e470 c20737a2

drivers/clk/imx/clk-imx25.c

+2 −16
Original line number Diff line number Diff line
@@ -96,13 +96,11 @@ static struct clk ** const uart_clks[] __initconst = { 
	NULL

};



static int __init __mx25_clocks_init(unsigned long osc_rate,

				     void __iomem *ccm_base)

static int __init __mx25_clocks_init(void __iomem *ccm_base)

{

	BUG_ON(!ccm_base);



	clk[dummy] = imx_clk_fixed("dummy", 0);

	clk[osc] = imx_clk_fixed("osc", osc_rate);

	clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL));

	clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL));

	clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
@@ -250,22 +248,10 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, 


static void __init mx25_clocks_init_dt(struct device_node *np)

{

	struct device_node *refnp;

	unsigned long osc_rate = 24000000;

	void __iomem *ccm;



	/* retrieve the freqency of fixed clocks from device tree */

	for_each_compatible_node(refnp, NULL, "fixed-clock") {

		u32 rate;

		if (of_property_read_u32(refnp, "clock-frequency", &rate))

			continue;



		if (of_device_is_compatible(refnp, "fsl,imx-osc"))

			osc_rate = rate;

	}



	ccm = of_iomap(np, 0);

	__mx25_clocks_init(osc_rate, ccm);

	__mx25_clocks_init(ccm);



	clk_data.clks = clk;

	clk_data.clk_num = ARRAY_SIZE(clk);

drivers/clk/imx/clk-imx51-imx53.c

+4 −4
Original line number Diff line number Diff line
@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np) 
						mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);

	clk[IMX5_CLK_LDB_DI0_GATE]	= imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);

	clk[IMX5_CLK_LDB_DI1_GATE]	= imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);

	clk[IMX5_CLK_IPU_DI0_SEL]	= imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,

						mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));

	clk[IMX5_CLK_IPU_DI1_SEL]	= imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,

						mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));

	clk[IMX5_CLK_IPU_DI0_SEL]	= imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,

						mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);

	clk[IMX5_CLK_IPU_DI1_SEL]	= imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,

						mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);

	clk[IMX5_CLK_TVE_EXT_SEL]	= imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,

						mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);

	clk[IMX5_CLK_TVE_GATE]		= imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);

drivers/clk/imx/clk-imx6q.c

+2 −1
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ static const char *cko_sels[] = { "cko1", "cko2", }; 
static const char *lvds_sels[] = {

	"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",

	"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",

	"pcie_ref_125m", "sata_ref_100m",

	"pcie_ref_125m", "sata_ref_100m",  "usbphy1", "usbphy2",

	"dummy", "dummy", "dummy", "dummy", "osc",

};

static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };

static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };

drivers/clk/imx/clk-imx6ul.c

+1 −3
Original line number Diff line number Diff line
@@ -399,9 +399,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	/* mask handshake of mmdc */

	writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);



	for (i = 0; i < ARRAY_SIZE(clks); i++)

		if (IS_ERR(clks[i]))

			pr_err("i.MX6UL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));

	imx_check_clocks(clks, ARRAY_SIZE(clks));



	clk_data.clks = clks;

	clk_data.clk_num = ARRAY_SIZE(clks);

drivers/clk/imx/clk-imx7d.c

+7 −4
Original line number Diff line number Diff line
@@ -833,10 +833,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) 


	clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);



	for (i = 0; i < ARRAY_SIZE(clks); i++)

		if (IS_ERR(clks[i]))

			pr_err("i.MX7D clk %d: register failed with %ld\n",

					i, PTR_ERR(clks[i]));

	clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk",

					 clks[IMX7D_ARM_A7_ROOT_CLK],

					 clks[IMX7D_ARM_A7_ROOT_SRC],

					 clks[IMX7D_PLL_ARM_MAIN_CLK],

					 clks[IMX7D_PLL_SYS_MAIN_CLK]);



	imx_check_clocks(clks, ARRAY_SIZE(clks));



	clk_data.clks = clks;

	clk_data.clk_num = ARRAY_SIZE(clks);