Commit c9531b4f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux into next/soc 

Merge "changes for Broadcom SoCs":

- Dan fixes an error path in the BCM63xx SMP code

- Ray adds the relevant Kconfig selects to enable the Broadcom NAND driver on Cygnus

- Kevin provides a change to the Broadcom GISB arbiter driver to make it work with
  MIPS-based big-endian STB SoCs (this was a long-standing change that had dependencies on
  code in drivers/of/*)

- Gregory enables the use of GPIOLIB for brcmstb SoCs and bumps the number of GPIOs for
  these platforms

* tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux:
  ARM: brcmstb: Add default gpio number
  ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIB
  bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties
  ARM: BCM: Enable NAND support for iProc SoCs
  ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()
parents 4fd8a5a5 b35d2e56

arch/arm/Kconfig

+2 −1
Original line number Original line Diff line number Diff line
@@ -1509,7 +1509,8 @@ config ARM_PSCI 
# selected platforms.

# selected platforms.

config ARCH_NR_GPIO

config ARCH_NR_GPIO

	int

	int

	default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ

	default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \

		ARCH_ZYNQ

	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \

	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \

		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210

		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210

	default 416 if ARCH_SUNXI

	default 416 if ARCH_SUNXI

arch/arm/mach-bcm/Kconfig

+2 −0
Original line number Original line Diff line number Diff line
@@ -19,6 +19,7 @@ config ARCH_BCM_IPROC 
	select ARCH_REQUIRE_GPIOLIB

	select ARCH_REQUIRE_GPIOLIB

	select ARM_AMBA

	select ARM_AMBA

	select PINCTRL

	select PINCTRL

	select MTD_NAND_BRCMNAND

	help

	help

	  This enables support for systems based on Broadcom IPROC architected SoCs.

	  This enables support for systems based on Broadcom IPROC architected SoCs.

	  The IPROC complex contains one or more ARM CPUs along with common

	  The IPROC complex contains one or more ARM CPUs along with common
@@ -144,6 +145,7 @@ config ARCH_BRCMSTB 
	select BRCMSTB_GISB_ARB

	select BRCMSTB_GISB_ARB

	select BRCMSTB_L2_IRQ

	select BRCMSTB_L2_IRQ

	select BCM7120_L2_IRQ

	select BCM7120_L2_IRQ

	select ARCH_WANT_OPTIONAL_GPIOLIB

	help

	help

	  Say Y if you intend to run the kernel on a Broadcom ARM-based STB

	  Say Y if you intend to run the kernel on a Broadcom ARM-based STB

	  chipset.

	  chipset.

arch/arm/mach-bcm/bcm63xx_pmb.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -150,7 +150,7 @@ int bcm63xx_pmb_power_on_cpu(struct device_node *dn) 
	 */

	 */

	ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl);

	ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl);

	if (ret)

	if (ret)

		return ret;

		goto out;





	if (ctrl & CPU_RESET_N(cpu)) {

	if (ctrl & CPU_RESET_N(cpu)) {

		pr_info("PMB: CPU%d is already powered on\n", cpu);

		pr_info("PMB: CPU%d is already powered on\n", cpu);

drivers/bus/brcmstb_gisb.c

+11 −2
Original line number Original line Diff line number Diff line
@@ -91,6 +91,7 @@ static const int gisb_offsets_bcm7445[] = { 
struct brcmstb_gisb_arb_device {

struct brcmstb_gisb_arb_device {

	void __iomem	*base;

	void __iomem	*base;

	const int	*gisb_offsets;

	const int	*gisb_offsets;

	bool		big_endian;

	struct mutex	lock;

	struct mutex	lock;

	struct list_head next;

	struct list_head next;

	u32 valid_mask;

	u32 valid_mask;
@@ -108,6 +109,9 @@ static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg) 
	if (offset == -1)

	if (offset == -1)

		return 1;

		return 1;





	if (gdev->big_endian)

		return ioread32be(gdev->base + offset);

	else

		return ioread32(gdev->base + offset);

		return ioread32(gdev->base + offset);

}

}
@@ -117,6 +121,10 @@ static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg) 




	if (offset == -1)

	if (offset == -1)

		return;

		return;



	if (gdev->big_endian)

		iowrite32be(val, gdev->base + reg);

	else

		iowrite32(val, gdev->base + reg);

		iowrite32(val, gdev->base + reg);

}

}
@@ -296,6 +304,7 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev) 
		return -EINVAL;

		return -EINVAL;

	}

	}

	gdev->gisb_offsets = of_id->data;

	gdev->gisb_offsets = of_id->data;

	gdev->big_endian = of_device_is_big_endian(dn);





	err = devm_request_irq(&pdev->dev, timeout_irq,

	err = devm_request_irq(&pdev->dev, timeout_irq,

				brcmstb_gisb_timeout_handler, 0, pdev->name,

				brcmstb_gisb_timeout_handler, 0, pdev->name,