Commit ca403b37 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Mauro Carvalho Chehab
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media: imx: imx7_mipi_csis: Update ISP_CONFIG macros for quad pixel mode 



The i.MX8MM expands the DOUBLE_CMPNT bit in the ISP_CONFIG register into
a two bits field that support quad pixel mode in addition to the single
and double modes. Update the ISP_CONFIG register macros to support this.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: default avatarRui Miguel Silva <rmfrfs@gmail.com>
Reviewed-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 7fe1de81

drivers/staging/media/imx/imx7-mipi-csis.c

+3 −1
Original line number Diff line number Diff line
@@ -166,7 +166,9 @@ 
#define MIPI_CSIS_ISP_CONFIG_CH(n)		(0x40 + (n) * 0x10)

#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK	(0xff << 24)

#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)	((x) << 24)

#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT		BIT(12)

#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE	(0 << 12)

#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL	(1 << 12)

#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD	(2 << 12)	/* i.MX8M[MNP] only */

#define MIPI_CSIS_ISPCFG_ALIGN_32BIT		BIT(11)

#define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT	(0x1e << 2)

#define MIPI_CSIS_ISPCFG_FMT_RAW8		(0x2a << 2)