Commit ca8a4ebc authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sme: Manually encode SME instructions 



As with SVE rather than impose ambitious toolchain requirements for SME
we manually encode the few instructions which we require in order to
perform the work the kernel needs to do. The instructions used to save
and restore context are provided as assembler macros while those for
entering and leaving streaming mode are done in asm volatile blocks
since they are expected to be used from C.

We could do the SMSTART and SMSTOP operations with read/modify/write
cycles on SVCR but using the aliases provided for individual field
accesses should be slightly faster. These instructions are aliases for
MSR but since our minimum toolchain requirements are old enough to mean
that we can't use the sX_X_cX_cX_X form and they always use xzr rather
than taking a value like write_sysreg_s() wants we just use .inst.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419112247.711548-7-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b4adc83b

arch/arm64/include/asm/fpsimd.h

+25 −0
Original line number Diff line number Diff line
@@ -249,6 +249,31 @@ static inline void sve_setup(void) { } 


#endif /* ! CONFIG_ARM64_SVE */



#ifdef CONFIG_ARM64_SME



static inline void sme_smstart_sm(void)

{

	asm volatile(__msr_s(SYS_SVCR_SMSTART_SM_EL0, "xzr"));

}



static inline void sme_smstop_sm(void)

{

	asm volatile(__msr_s(SYS_SVCR_SMSTOP_SM_EL0, "xzr"));

}



static inline void sme_smstop(void)

{

	asm volatile(__msr_s(SYS_SVCR_SMSTOP_SMZA_EL0, "xzr"));

}



#else



static inline void sme_smstart_sm(void) { }

static inline void sme_smstop_sm(void) { }

static inline void sme_smstop(void) { }



#endif /* ! CONFIG_ARM64_SME */



/* For use by EFI runtime services calls only */

extern void __efi_fpsimd_begin(void);

extern void __efi_fpsimd_end(void);

arch/arm64/include/asm/fpsimdmacros.h

+54 −0
Original line number Diff line number Diff line
@@ -93,6 +93,12 @@ 
	.endif

.endm



.macro _sme_check_wv v

	.if (\v) < 12 || (\v) > 15

		.error "Bad vector select register \v."

	.endif

.endm



/* SVE instruction encodings for non-SVE-capable assemblers */

/* (pre binutils 2.28, all kernel capable clang versions support SVE) */
@@ -174,6 +180,54 @@ 
		| (\np)

.endm



/* SME instruction encodings for non-SME-capable assemblers */

/* (pre binutils 2.38/LLVM 13) */



/* RDSVL X\nx, #\imm */

.macro _sme_rdsvl nx, imm

	_check_general_reg \nx

	_check_num (\imm), -0x20, 0x1f

	.inst	0x04bf5800			\

		| (\nx)				\

		| (((\imm) & 0x3f) << 5)

.endm



/*

 * STR (vector from ZA array):

 *	STR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]

 */

.macro _sme_str_zav nw, nxbase, offset=0

	_sme_check_wv \nw

	_check_general_reg \nxbase

	_check_num (\offset), -0x100, 0xff

	.inst	0xe1200000			\

		| (((\nw) & 3) << 13)		\

		| ((\nxbase) << 5)		\

		| ((\offset) & 7)

.endm



/*

 * LDR (vector to ZA array):

 *	LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]

 */

.macro _sme_ldr_zav nw, nxbase, offset=0

	_sme_check_wv \nw

	_check_general_reg \nxbase

	_check_num (\offset), -0x100, 0xff

	.inst	0xe1000000			\

		| (((\nw) & 3) << 13)		\

		| ((\nxbase) << 5)		\

		| ((\offset) & 7)

.endm



/*

 * Zero the entire ZA array

 *	ZERO ZA

 */

.macro zero_za

	.inst 0xc00800ff

.endm



.macro __for from:req, to:req

	.if (\from) == (\to)

		_for__body %\from